AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

Download PDF
ID 776775
Date 5/19/2023
Public
Document Table of Contents
Document Table of Contents x
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs x
AC Coupling and DC Coupling TDS I/O On-Chip Termination TDS I/O External Termination Termination and Biasing Schemes for TDS Transmitters and Receivers Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter Summary Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
AC Coupling and DC Coupling x
Capacitors and Components Selection
Termination and Biasing Schemes for TDS Transmitters and Receivers x
Schematic Topology for Transmitter and Receiver Buffers Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver x
Simulation Results
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter x
Simulation Results
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

TDS I/O External Termination

Analyze the electrical specification requirement of the LVDS interface and ensure that the common-mode voltage for your LVDS data rate conforms to the data sheet specification.
  • Use AC coupling and external voltage bias circuitry if the common-mode voltage of the output buffer does not match the differential receiver input common-mode voltage.
  • Consider using a dedicated VICM voltage supply for wide LVDS interfaces that share a common VICM reference voltage.
Note: Intel recommends that you use SPICE or IBIS models to verify your AC-coupled or DC-coupled termination.
Related Information
Level Two Title