AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

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ID 776775
Date 5/19/2023
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Document Table of Contents
Document Table of Contents x
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs x
AC Coupling and DC Coupling TDS I/O On-Chip Termination TDS I/O External Termination Termination and Biasing Schemes for TDS Transmitters and Receivers Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter Summary Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
AC Coupling and DC Coupling x
Capacitors and Components Selection
Termination and Biasing Schemes for TDS Transmitters and Receivers x
Schematic Topology for Transmitter and Receiver Buffers Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver x
Simulation Results
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter x
Simulation Results
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL

These recommended topologies are based on data sheet specifications.
Note: In your design, ensure that you meet the VID and VICM specifications of the TDS device ( Intel Agilex® 7 M-Series or Intel Agilex® 5 FPGA).
Figure 1. AC-Coupled LVDS, RSDS, or Mini-LVDS Transmitter Interface to FPGA TDS ReceiverIn this figure, the JEDEC-compliant transmitter is the Intel® Arria® 10 FPGA while the TDS receiver is the Intel Agilex® 7 M-Series or Intel Agilex® 5 FPGA.
Figure 2. FPGA 1.3 V TDS Transmitter Interface to LVDS or LVPECL Receiver—Data Rate ≤ 700 MbpsIn this figure, the TDS transmitter is the Intel Agilex® 7 M-Series or Intel Agilex® 5 FPGA while the JEDEC-compliant receiver is the Intel® Arria® 10 FPGA.


Figure 3. FPGA 1.3 V TDS Transmitter Interface to LVDS or LVPECL Receiver—Data Rate > 700 MbpsIn this figure, the TDS transmitter is the Intel Agilex® 7 M-Series or Intel Agilex® 5 FPGA while the JEDEC-compliant receiver is the Intel® Arria® 10 FPGA. This figure is for data rate > 700 Mbps
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