Visible to Intel only — GUID: yax1683754180864
Ixiasoft
AC Coupling and DC Coupling
TDS I/O On-Chip Termination
TDS I/O External Termination
Termination and Biasing Schemes for TDS Transmitters and Receivers
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter
Summary
Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
Visible to Intel only — GUID: yax1683754180864
Ixiasoft
Simulation Results
Figure 11. FPGA 1.3 V TDS Transmitter Interface with LVDS, Receiver—600 MbpsThe eye diagram was plotted and measured at 600 Mbps.
Figure 12. FPGA 1.3 V TDS Transmitter Interface with LVDS Receiver—750 MbpsThe eye diagram was plotted and measured at 750 Mbps.