AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

ID 776775
Date 5/19/2023
Public

Simulation Results

Figure 11. FPGA 1.3 V TDS Transmitter Interface with LVDS, Receiver—600 MbpsThe eye diagram was plotted and measured at 600 Mbps.


Figure 12. FPGA 1.3 V TDS Transmitter Interface with LVDS Receiver—750 MbpsThe eye diagram was plotted and measured at 750 Mbps.