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Ixiasoft
AC Coupling and DC Coupling
TDS I/O On-Chip Termination
TDS I/O External Termination
Termination and Biasing Schemes for TDS Transmitters and Receivers
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter
Summary
Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
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Ixiasoft
Schematic Topology for Transmitter and Receiver Buffers
Implement DC coupling if the signal swing and offset voltage requirement are within the Intel Agilex® 7 M series and Intel Agilex® 5 TDS standard specifications. Otherwise, implement AC coupling and external bias circuitry.