AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

ID 776775
Date 5/19/2023
Public

Schematic Topology for Transmitter and Receiver Buffers

Implement DC coupling if the signal swing and offset voltage requirement are within the Intel Agilex® 7 M series and Intel Agilex® 5 TDS standard specifications. Otherwise, implement AC coupling and external bias circuitry.