AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

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ID 776775
Date 5/19/2023
Public
Document Table of Contents
Document Table of Contents x
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs x
AC Coupling and DC Coupling TDS I/O On-Chip Termination TDS I/O External Termination Termination and Biasing Schemes for TDS Transmitters and Receivers Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter Summary Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
AC Coupling and DC Coupling x
Capacitors and Components Selection
Termination and Biasing Schemes for TDS Transmitters and Receivers x
Schematic Topology for Transmitter and Receiver Buffers Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver x
Simulation Results
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter x
Simulation Results
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

Summary

From the results of the simulations based on the recommended topologies, the VICM and and VID voltages met the specific requirements of the interfaces.

The recommended component values in the topologies are based on ideal case conditions. You may need to use different VICM voltages depending on your use cases and conditions.

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