AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

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ID 776775
Date 5/19/2023
Public
Document Table of Contents
Document Table of Contents x
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs x
AC Coupling and DC Coupling TDS I/O On-Chip Termination TDS I/O External Termination Termination and Biasing Schemes for TDS Transmitters and Receivers Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter Summary Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
AC Coupling and DC Coupling x
Capacitors and Components Selection
Termination and Biasing Schemes for TDS Transmitters and Receivers x
Schematic Topology for Transmitter and Receiver Buffers Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver x
Simulation Results
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter x
Simulation Results
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs use the True Differential Signaling (TDS) I/O standard to interface with differential signaling I/O standards. The TDS transmitters and receivers, with AC or DC coupling configurations, require different termination and biasing schemes for different I/O standards.

This application note demonstrates the recommended termination and biasing by interfacing an Intel Agilex® 7 M-Series FPGA with the Intel® Arria® 10 FPGA. The Intel® Arria® 10 FPGA represents a device that supports JEDEC-compliant LVDS, RSDS, mini-LVDS, and LVPECL I/O standards.

Table 1.  Differential Signaling Interfaces Supported by TDS
Interface Application
LVDS General applications
RSDS Flat panel display
Mini-LVDS TFT LCD panel column driver
LVPECL Video graphics and clock distribution
Table 2.  TDS I/O Standards for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
I/O Standard Direction Voltages (V)
VID VICM VOD VOCM
Min. Max. Min. Max. Min. Max. Min. Typ. Max.
1.3 V TDS

Transmit

Receive

 0.1 0.454 0.5 1.375

1

0.247 0.36 0.9 1.0 1.1
1.2 V TDS Receive 0.1 0.454 0.8 0.95 — — — — —
1.1 V TDS Receive 0.1 0.454 0.8 0.95 — — — — —
1.05 V TDS Receive 0.1 0.454 0.8 0.95 — — — — —

Section Content
AC Coupling and DC Coupling
TDS I/O On-Chip Termination
TDS I/O External Termination
Termination and Biasing Schemes for TDS Transmitters and Receivers
Simulation: Intel Agilex 7 M-Series FPGA as TDS Receiver
Simulation: Intel Agilex 7 M-Series FPGA as TDS Transmitter
Summary
Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Intel Agilex 7 M-Series and Intel Agilex 5 FPGAs

Related Information
1 The VICM (DC) voltage must not exceed 1.2 V if you disable on-chip differential termination (RD OCT) to use external on-board termination.
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