1.2.10. Power Supply Pins
Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Note: Altera recommends you to generate a .pin file from the Quartus® Prime Fitter to verify power pin assignment. Altera also recommends using this .pin file to determine if it is safe to power down or ground certain power supplies for your specific design. This step informs you to make the appropriate design choices for unused power supplies for your design.
| Pin Name | Pin Functions | Pin Description | Connection Guidelines |
|---|---|---|---|
| VCCP | Power | VCCP supplies power to the periphery. | VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator. For details about the recommended operating conditions, refer to the Electrical Characteristics section in the Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series . Use the Power and Thermal Calculator and the Quartus® Prime Power Analyzer to determine the current requirements for VCCP and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board. |
| VCC | Power | VCC supplies power to the core. | VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator. For details about the recommended operating conditions, refer to the Electrical Characteristics section in the Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series . Use the Power and Thermal Calculator and the Quartus® Prime Power Analyzer to determine the current requirements for VCC and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board. |
| VCCPT | Power | Power supply for the IOPLL, programmable power technology, and I/O pre-drivers. | Connect VCCPT to a 1.8-V low noise switching regulator. You have the option to source the following from the same regulator as VCCPT:
Voltage spike ringing may be observed on VCCPT during device power-down sequencing if VCC is powered down before VCCPT, with the magnitude of the voltage spike ringing higher than VCCPT. This is the expected behavior and causes neither any functional failure nor reliability concerns to the device. For more details about the decoupling recommendations for this voltage rail, refer to Agilex™ 7 Power Distribution Network Design Guidelines . For the power rail sharing, refer to the Agilex™ 7 M-Series Power Supply Sharing Guidelines section. |
| VCCRCORE | Power | CRAM power supply. | Connect the VCCRCORE to 1.2 V power supply. You have the option to source VCCRCORE from the same regulator as VCCIO_PIO only when you are using 1.2 V for VCCIO_PIO. |
| VCCH | Power | Analog Interface Bridge (AIB) and digital transceiver power supply. | Connect all VCCH pins to a 0.8 V low noise switching power supply for Agilex™ 7 M-Series devices. For more details, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series . |
| VCCH_SDM | Power | Voltage rail sense. | Must connect this sense to the VCC_HSSI_GXR rail for the Agilex™ 7 M-Series devices with F-Tile and R-Tile if VCC_HSSI_GXR is powered, and connect it to VCCH if all R-Tiles are unused and VCC_HSSI_GXR is tied to GND. Must connect this sense to the VCCH rail for the Agilex™ 7 M-Series device with F-Tile only. |
| VCCIO_PIO_2[A,B,C,D,E,F]T VCCIO_PIO_2[A,B,C,D,E,F]B VCCIO_PIO_3[A,B,C,D,E,F]T VCCIO_PIO_3[A,B,C,D,E,F]B |
Power | These are the supply voltage pins for the I/O banks. Each sub-bank can support a different voltage level. Supported VCCIO standards include the following:
For more information about the supported pins, refer to the device pin-out file. |
Connect these pins to a 1.05 V, 1.1 V, 1.2 V, or 1.3 V power supplies, depending on the I/O standard required by the specific sub-bank. If you plan to use the I/O bank in the future, connect the unused I/O bank power to 1.05 V, 1.1 V, 1.2 V, or 1.3 V. However, if you do not plan to use the I/O bank in the future, connect the unused I/O bank power to GND and I/O pins floating. Do not leave the VCCIO_PIO floating. When the entire GPIO-B bank is unused, you may connect the VCCIO_PIO of the unused GPIO-B bank to 0 V, 1.05 V, 1.1 V, 1.2 V, or 1.3 V. If only one of the sub-bank within the same GPIO-B bank is unused, you must connect the VCCIO_PIO of the unused sub-bank to the same VCCIO_PIO voltage level as the other actively utilized sub-bank. You may supply the VCCIO_PIO voltage rail of a sub-bank with a ±5% voltage tolerance only if the entire sub-bank is operating in any of LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, or 1.2 V True Differential Signaling input standard, PHY Lite mode, or GPIO mode. Otherwise, you must supply the VCCIO_PIO voltage rail with ±3% voltage supply tolerance. For production device, you have option to connect VCCIO_PIO_T and VCCIO_PIO_B in the same I/O bank with different voltage level, for example, VCCIO_PIO_2AT (1.2 V) and VCCIO_PIO_2AB (1.1 V). For ES device, you must connect VCCIO_PIO_T and VCCIO_PIO_B in the same I/O bank with the same voltage level, for example, VCCIO_PIO_2AT (1.2 V) and VCCIO_PIO_2AB (1.2 V). During the power-up sequence only, a transient current whose magnitude is less than the VCCIO_PIO operating static current may be observed as the VCCIO_PIO transistors become operational. This is the expected behavior and causes neither any functional failure nor reliability concerns to the device if the power-up or power-down sequence is followed. For more details, refer to the Agilex™ 7 M-Series Sensor Monitoring System chapter in the Agilex™ 7 Power Management User Guide . For the power rail sharing, refer to the Agilex™ 7 M-Series Power Supply Sharing Guidelines. |
| VCCIO_PIO_SDM | Power | VCCIO_PIO voltage rail sense line. | Connect these pins to VCCIO_PIO_3AT at 1.2 V when you use Avalon® streaming x16/x32 for FPGA configuration. Connect these pins to VCCRCORE if you are not using Avalon® streaming x16/x32 for FPGA configuration. |
| VCCIO_SDM | Power | Configuration pins power supply. | Connect these pins to a 1.8-V power supply. You have an option to share the same regulator with VCCPT. For more details about the decoupling recommendations for this voltage rail, refer to the Agilex™ 7 Power Distribution Network Design Guidelines . For the power rail sharing, refer to the Agilex™ 7 M-Series Power Supply Sharing Guidelines. |
| VCCPLLDIG_SDM | Power | SDM block PLL power pins. | VCCPLLDIG_SDM must be sourced from the same regulator as VCCL_SDM with proper isolation filtering. |
| VCCL_SDM | Power | SDM power supply. | Connect these pins to a 0.8 V power supply. You have option to share the same regulator with VCCH. |
| VCCBAT | Power | Battery back-up power supply for device security Advanced Encryption Standard, Battery-backed RAM (AES BBRAM) key register. | When using the device security AES BBRAM key, connect this pin to a non-volatile battery power source in the range of 1.0 V to 1.8 V. A series RC (R=10 KΩ, C=1uF) circuit must be added to VCCBAT rail, the 10 KΩ resistor is connected in series between the battery source and VCCBAT. The 1uF capacitor is connected between VCCPT and GND. For more information about the schematic diagram, refer to Agilex™ 7 Power Distribution Network Design Guidelines . Provide a minimum decoupling of 47 nF for the VCCBAT power rail near the VCCBAT pin. When not using the AES BBRAM key, tie this pin to GND. |
| VCCPLL_SDM | Power | VCCPLL_SDM supplies analog power to the SDM block PLLs. | With proper isolation filtering, you have the option to source VCCPLL_SDM from the same regulator as VCCPT. Decoupling for these pins depends on the design decoupling requirements of the specific board. |
| GND | Ground | Device ground pins. | Connect all GND pins to the board ground plane. |
| VCCLSENSE | Output | Differential sense line to external regulator. | VCCLSENSE and GNDSENSE are differential remote sense pins for the VCC power. Connect your regulators’ differential remote sense lines to the respective VCCLSENSE and GNDSENSE pins. This compensates for the DC IR drop associated with the PCB and device package from the VCC power. Route these connections as differential pair traces and keep them isolated from any other noise source. You must connect the VCCLSENSE and GNDSENSE lines to the regulator’s remote sense inputs. |
| GNDSENSE | |||
| VCCADC | Power | Analog-to-digital converter (ADC) power pin for the voltage sensors. | You must supply a low noise 1.8-V power supply to this pin if you are using the internal voltage sensors of the Agilex™ 7 M-Series device. Tie this pin to VCCPT with proper isolation filtering. |
| VCCFUSEWR_SDM | Power | The required power supply to program (write) the optional, one-time programmable eFuses. These eFuses are an integral part of the Agilex™ 7 M-Series security architecture. | Connect this pin to 1.8 V. Must source VCCFUSEWR_SDM and VCCPT from the same 1.8 V regulator. |
| VCCLPLL_NOC_[T,B] | Power | I/O and digital power pin for network on a chip (NoC). | Connect these pins to a 0.8-V power supply. You have option to share the same regulator with VCCH. |
| VCCPLLDIG_NOC_[T,B] | Power | Digital power pin for NoC. | VCCPLLDIG_NOC must be sourced from the same regulator as VCCLPLL_NOC with proper isolation filtering. |
| VCCPLL_NOC_[T,B] | Power | Analog power pin for NoC. | Connect these pins to a 1.8-V power supply. You have option to share the same regulator as VCCPT with proper isolation filtering. |
| VCCIO_NOC_[T,B] | Power | I/O power pin for NoC. | Connect these pins to a 1.8-V power supply. You have option to share the same regulator with VCCPT. |