Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

Download PDF
ID 776197
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series x
1.1. Pins Status for Agilex™ 7 M-Series Devices 1.2. Agilex™ 7 M-Series FPGA Core Pins 1.3. Agilex™ 7 M-Series HBM2E Pins 1.4. Agilex™ 7 M-Series F-Tile Pins 1.5. Agilex™ 7 M-Series R-Tile Pins 1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins 1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines 1.8. Notes to Agilex™ 7 M-Series Device Family Pin Connection Guidelines 1.9. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1.2. Agilex™ 7 M-Series FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 M-Series HBM2E Pins x
1.3.1. HBM2E Power Supply Pins 1.3.2. HBM2E Signal Pins
1.4. Agilex™ 7 M-Series F-Tile Pins x
1.4.1. F-Tile Power Supply Pins 1.4.2. F-Tile Transceiver Pins
1.5. Agilex™ 7 M-Series R-Tile Pins x
1.5.1. R-Tile Power Supply Pins 1.5.2. R-Tile Transceiver Pins
1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins
1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines x
1.7.1. Example 1— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR4 1.7.2. Example 2— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR5 1.7.3. Example 3— Agilex™ 7 M-Series Devices with R-Tile and F-Tile, Without HBM2E Using DDR4 1.7.4. Example 4— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR4 1.7.5. Example 5— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR5 1.7.6. Example 6— Agilex™ 7 M-Series Devices with F-Tile only and Without HBM2E Using DDR5
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

1.3.2. HBM2E Signal Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Pin Name Pin Functions Pin Description Connection Guidelines
REXT_UIB[00,01] Input RCOMP external register pin for PSIO/PDIO TX Calibration of UIB. Connect these pins to GND through a 240 Ω resistor.
REFCLK_P_UIB[00,01] Input Dedicated positive high speed differential reference clock pin for UIB PLL.

Connect this pin to the positive terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

  • 20 ps peak-to-peak
  • 1.42 ps RMS at 1e-12 BER
  • 1.22 ps at 1e-16 BER

You must provide a stable reference clock to this pin before device configuration begins when the high-bandwidth memory (HBM2E) IP is included in your design.

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

REFCLK_N_UIB[00,01] Input Dedicated complement high speed differential reference clock pin for UIB PLL.

Connect this pin to the negative terminal of an LVDS clock source within the range of 10 MHz to 325 MHz. The frequency selected must match the available options provided in the Quartus® Prime HBM2E interface PLL Reference Clock Frequency selection dialog box. Only DC-coupling is supported. The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

  • 20 ps peak-to-peak
  • 1.42 ps RMS at 1e-12 BER
  • 1.22 ps at 1e-16 BER

You must provide a stable reference clock to this pin before device configuration begins when the high-bandwidth memory (HBM2E) IP is included in your design.

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

REFCLK_P_FBR[0,1]_UIB[00,01] Input

Dedicated positive high speed differential reference clock pin for fabric PLL.

The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

  • 20 ps peak-to-peak
  • 1.42 ps RMS at 1e-12 BER
  • 1.22 ps at 1e-16 BER

You must provide a stable reference clock to this pin before device configuration begins.

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

REFCLK_N_FBR[0,1]_UIB[00,01] Input Dedicated complement high speed differential reference clock pin for fabric PLL.

The peak-to-peak jitter of this clock must meet or exceed the following jitter requirements for frequency bandwidth from 10 kHz to 1/2 of the frequency chosen:

  • 20 ps peak-to-peak
  • 1.42 ps RMS at 1e-12 BER
  • 1.22 ps at 1e-16 BER

You must provide a stable reference clock to this pin before device configuration begins.

Connect directly to GND if unused.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.

Level Two Title