Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

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ID 776197
Date 6/12/2024
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Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series x
1.1. Pins Status for Agilex™ 7 M-Series Devices 1.2. Agilex™ 7 M-Series FPGA Core Pins 1.3. Agilex™ 7 M-Series HBM2E Pins 1.4. Agilex™ 7 M-Series F-Tile Pins 1.5. Agilex™ 7 M-Series R-Tile Pins 1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins 1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines 1.8. Notes to Agilex™ 7 M-Series Device Family Pin Connection Guidelines 1.9. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1.2. Agilex™ 7 M-Series FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 M-Series HBM2E Pins x
1.3.1. HBM2E Power Supply Pins 1.3.2. HBM2E Signal Pins
1.4. Agilex™ 7 M-Series F-Tile Pins x
1.4.1. F-Tile Power Supply Pins 1.4.2. F-Tile Transceiver Pins
1.5. Agilex™ 7 M-Series R-Tile Pins x
1.5.1. R-Tile Power Supply Pins 1.5.2. R-Tile Transceiver Pins
1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins
1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines x
1.7.1. Example 1— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR4 1.7.2. Example 2— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR5 1.7.3. Example 3— Agilex™ 7 M-Series Devices with R-Tile and F-Tile, Without HBM2E Using DDR4 1.7.4. Example 4— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR4 1.7.5. Example 5— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR5 1.7.6. Example 6— Agilex™ 7 M-Series Devices with F-Tile only and Without HBM2E Using DDR5
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

1.3.1. HBM2E Power Supply Pins

Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 12.  HBM2E Power Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCIO_UIB[00,01] Power I/O power supply for UIB.

Connect these pins to a 1.2-V power supply. You have the option to share the same regulator with VCCIO_PIO when VCCIO_PIO is connected to 1.2-V.

For more details about the decoupling recommendations for this voltage rail, refer to the Agilex™ 7 Power Distribution Network Design Guidelines .

VCCM_PUMP_HBM_U[50,51] Power Pump power supply for HBM2E.

Connect these pins to a 2.5-V power supply.

VCCIOSENSE_B_UIB

Output

Differential sense line to external regulator.

Connect the differential remote sense lines of the regulator to the respective VCCIOSENSE_B_UIB and VSSIOSENSE_B_UIB pins. This compensates for the DC IR drop associated with the PCB and device package from the VCCIO_UIB_00 power. Route these connections as differential pair traces and keep them isolated from any other noise source.

Connect VCCIOSENSE_B_UIB to VCCIO_UIB_00 and tie VSSIOSENSE_B_UIB to GND if unused.

VSSIOSENSE_B_UIB
VCCIOSENSE_T_UIB Output Differential sense line to external regulator.

Connect the differential remote sense lines of the regulator to the respective VCCIOSENSE_T_UIB and VSSIOSENSE_T_UIB pins. This compensates for the DC IR drop associated with the PCB and device package from the VCCIO_UIB_01 power. Route these connections as differential pair traces and keep them isolated from any other noise source.

Connect VCCIOSENSE_T_UIB to VCCIO_UIB_01 and tie VSSIOSENSE_T_UIB to GND if unused.

VSSIOSENSE_T_UIB
VCCMSENSE_B_UIB Output Differential sense line to external regulator.

Connect the differential remote sense lines of the regulator to the respective VCCMSENSE_B_UIB and VSSMSENSE_B_UIB pins. This compensates for the DC IR drop associated with the PCB and device package from the VCCM_PUMP_HBM_U50 power. Route these connections as differential pair traces and keep them isolated from any other noise source.

Connect VCCMSENSE_B_UIB to VCCM_PUMP_HBM_U50 and tie VSSMSENSE_B_UIB to GND if unused.

VSSMSENSE_B_UIB
VCCMSENSE_T_UIB Output Differential sense line to external regulator.

Connect the differential remote sense lines of the regulator to the respective VCCMSENSE_T_UIB and VSSMSENSE_T_UIB pins. This compensates for the DC IR drop associated with the PCB and device package from the VCCM_PUMP_HBM_U51 power. Route these connections as differential pair traces and keep them isolated from any other noise source.

Connect VCCMSENSE_T_UIB to VCCM_PUMP_HBM_U51 and tie VSSMSENSE_T_UIB to GND if unused.

VSSMSENSE_T_UIB
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