Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

Download PDF
ID 776197
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series x
1.1. Pins Status for Agilex™ 7 M-Series Devices 1.2. Agilex™ 7 M-Series FPGA Core Pins 1.3. Agilex™ 7 M-Series HBM2E Pins 1.4. Agilex™ 7 M-Series F-Tile Pins 1.5. Agilex™ 7 M-Series R-Tile Pins 1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins 1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines 1.8. Notes to Agilex™ 7 M-Series Device Family Pin Connection Guidelines 1.9. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1.2. Agilex™ 7 M-Series FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 M-Series HBM2E Pins x
1.3.1. HBM2E Power Supply Pins 1.3.2. HBM2E Signal Pins
1.4. Agilex™ 7 M-Series F-Tile Pins x
1.4.1. F-Tile Power Supply Pins 1.4.2. F-Tile Transceiver Pins
1.5. Agilex™ 7 M-Series R-Tile Pins x
1.5.1. R-Tile Power Supply Pins 1.5.2. R-Tile Transceiver Pins
1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins
1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines x
1.7.1. Example 1— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR4 1.7.2. Example 2— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR5 1.7.3. Example 3— Agilex™ 7 M-Series Devices with R-Tile and F-Tile, Without HBM2E Using DDR4 1.7.4. Example 4— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR4 1.7.5. Example 5— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR5 1.7.6. Example 6— Agilex™ 7 M-Series Devices with F-Tile only and Without HBM2E Using DDR5
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

1.6.6. HPS NAND Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 22.  HPS NAND Pins
HPS Pin Functions Pin Description and Connection Guidelines Pin Type Valid Assignments (select from one of the groups)
Group 1 Group 2
NAND_ADQ0 NAND Data Bit 0. I/O HPS_IOA_1 HPS_IOB_1
NAND_ADQ1 NAND Data Bit 1. I/O HPS_IOA_2 HPS_IOB_2
NAND_WE_N

NAND Write Enable.

This is an active-low signal.

 Output HPS_IOA_3 HPS_IOB_3
NAND_RE_N

NAND Read Enable.

This is an active-low signal.

 Output HPS_IOA_4 HPS_IOB_4
NAND_WP_N NAND Write Protect. Output HPS_IOA_5 HPS_IOB_5
NAND_ADQ2 NAND Data Bit 2. I/O HPS_IOA_6 HPS_IOB_6
NAND_ADQ3 NAND Data Bit 3. I/O HPS_IOA_7 HPS_IOB_7
NAND_CLE NAND Command Latch Enable. Output HPS_IOA_8 HPS_IOB_8
NAND_ADQ4 NAND Data Bit 4. I/O HPS_IOA_9 HPS_IOB_9
NAND_ADQ5 NAND Data Bit 5. I/O HPS_IOA_10 HPS_IOB_10
NAND_ADQ6 NAND Data Bit 6. I/O HPS_IOA_11 HPS_IOB_11
NAND_ADQ7 NAND Data Bit 7. I/O HPS_IOA_12 HPS_IOB_12
NAND_ALE NAND Address Latch Enable. Output HPS_IOA_13 HPS_IOB_13
NAND_RB

NAND Ready/Busy.

Connect this pin through a pull-up resistor to VCCIO_HPS. For more information of the pull-up resistor value, refer to the NAND flash specification.

Input HPS_IOA_14 HPS_IOB_14
NAND_CE_N

NAND Chip Enable.

This is an active-low signal.

 Output HPS_IOA_15 HPS_IOB_15
NAND_ADQ8 NAND Data Bit 8. I/O HPS_IOA_17 HPS_IOB_17
NAND_ADQ9 NAND Data Bit 9. I/O HPS_IOA_18 HPS_IOB_18
NAND_ADQ10 NAND Data Bit 10. I/O HPS_IOA_19 HPS_IOB_19
NAND_ADQ11 NAND Data Bit 11. I/O HPS_IOA_20 HPS_IOB_20
NAND_ADQ12 NAND Data Bit 12. I/O HPS_IOA_21 HPS_IOB_21
NAND_ADQ13 NAND Data Bit 13. I/O HPS_IOA_22 HPS_IOB_22
NAND_ADQ14 NAND Data Bit 14. I/O HPS_IOA_23 HPS_IOB_23
NAND_ADQ15 NAND Data Bit 15. I/O HPS_IOA_24 HPS_IOB_24
Level Two Title