Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

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ID 776197
Date 11/04/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series x
1.1. Pins Status for Agilex™ 7 M-Series Devices 1.2. Agilex™ 7 M-Series FPGA Core Pins 1.3. Agilex™ 7 M-Series HBM2E Pins 1.4. Agilex™ 7 M-Series F-Tile Pins 1.5. Agilex™ 7 M-Series R-Tile Pins 1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins 1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines 1.8. Notes to Agilex™ 7 M-Series Device Family Pin Connection Guidelines 1.9. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1.2. Agilex™ 7 M-Series FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 M-Series HBM2E Pins x
1.3.1. HBM2E Power Supply Pins 1.3.2. HBM2E Signal Pins
1.4. Agilex™ 7 M-Series F-Tile Pins x
1.4.1. F-Tile Power Supply Pins 1.4.2. F-Tile Transceiver Pins
1.5. Agilex™ 7 M-Series R-Tile Pins x
1.5.1. R-Tile Power Supply Pins 1.5.2. R-Tile Transceiver Pins
1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins
1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines x
1.7.1. Example 1— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR4 1.7.2. Example 2— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR5 1.7.3. Example 3— Agilex™ 7 M-Series Devices with R-Tile and F-Tile, Without HBM2E Using DDR4 1.7.4. Example 4— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR4 1.7.5. Example 5— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR5 1.7.6. Example 6— Agilex™ 7 M-Series Devices with F-Tile only and Without HBM2E Using DDR5
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

1.4.1. F-Tile Power Supply Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 13.  F-Tile Power Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCC_HSSI_GXF[L,R] Power

F-Tile digital 0.8-V logic.

For more information about the supported pins, refer to the device pin-out file.

Connect VCC_HSSI_GXF to low noise switching regulator.

Refer to Agilex™ 7 Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if this tile is not used.

VCCH_FGT_GXF[L,R] Power

F-Tile general-purpose transceiver (FGT) digital 1.8-V logic.

For more information about the supported pins, refer to the device pin-out file.

VCCH_FGT_GXF should share 1.8-V rail with VCCPT through a proper isolation filtering.

Refer to Agilex™ 7 Power Distribution Network Design Guidelines for fitter details and decoupling capacitor requirement.

Tie to GND if this tile is not used.

VCCEHT_FHT_GXF[L,R] Power

F-Tile high-speed transceiver (FHT) digital 1.5-V logic.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCEHT_FHT_GXF to dedicated regulator.

Refer to Agilex™ 7 Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if there is no FHT channel used.

VCCERT_FGT_GXF[L,R] Power

F-Tile FGT analog 1.0-V logic.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCERT_FGT_GXF to dedicated regulator.

Refer to Agilex™ 7 Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if this Tile is not used.

VCCERT1_FHT_GXF[L,R] Power

F-Tile FHT analog 1.0-V supply 1.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCERT1_FHT_GXF to dedicated regulator. You have an option to share the same regulator as VCCERT_FGT_GXF.

Refer to Agilex™ 7 Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if there is no FHT channel used.

VCCERT2_FHT_GXF[L,R] Power

F-Tile FHT analog 1.0-V supply 2.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCERT2_FHT_GXF to dedicated regulator. You have an option to share the same regulator as VCCERT_FGT_GXF.

Refer to Agilex™ 7 Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if there is no FHT channel used.

VCCFUSECORE_GXF[L,R] Power

F-Tile fuse sense 1.0-V supply.

For more information about the supported pins, refer to the device pin-out file.

VCCFUSECORE_GXF should share 1.0-V rail from power group1.

Refer to Agilex™ 7 Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if this tile is not used.

VCCFUSEWR_GXF[L,R] Power

F-Tile fuse sense 1.0-V supply.

For more information about the supported pins, refer to the device pin-out file.

VCCFUSEWR_GXF should share 1.0-V rail from power group.

Refer to Agilex™ 7 Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if this tile is not used.
VCCCLK_GXF[L,R] Power

F-Tile1.8-V supply.

For more information about the supported pins, refer to the device pin-out file.

VCCCLK_GXF should share 1.8-V rail with VCCPT through ferrite bead.

Refer to Agilex™ 7 Power Distribution Network Design Guidelines for filter details and decoupling capacitor requirement.

Tie to GND if this tile is not used.

VCC_SENSE_FHT_GXF Power Sense Differential sense line to external regulator.

VCC_SENSE_FHT_GXF and VSS_SENSE_FHT_GXF are differential remote sense pins for the VCCERT1_FHT_GXF power. Connect the differential remote sense lines of the regulator to the respective VCC_SENSE_FHT_GXF and VSS_SENSE_FHT_GXF pins. This compensates for the DC IR drop associated with the PCB and device package from the VCCERT1_FHT_GXF power. Route these connections as differential pair traces and keep them isolated from any other noise source.

You must connect the VCC_SENSE_FHT_GXF and VSS_SENSE_FHT_GXF lines to the remote sense inputs of the regulator.

Connect VCC_SENSE_FHT_GXF to VCCERT1_FHT_GXF and tie VSS_SENSE_FHT_GXF to GND if unused.

VSS_SENSE_FHT_GXF
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