Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

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ID 776197
Date 11/04/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series x
1.1. Pins Status for Agilex™ 7 M-Series Devices 1.2. Agilex™ 7 M-Series FPGA Core Pins 1.3. Agilex™ 7 M-Series HBM2E Pins 1.4. Agilex™ 7 M-Series F-Tile Pins 1.5. Agilex™ 7 M-Series R-Tile Pins 1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins 1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines 1.8. Notes to Agilex™ 7 M-Series Device Family Pin Connection Guidelines 1.9. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1.2. Agilex™ 7 M-Series FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 M-Series HBM2E Pins x
1.3.1. HBM2E Power Supply Pins 1.3.2. HBM2E Signal Pins
1.4. Agilex™ 7 M-Series F-Tile Pins x
1.4.1. F-Tile Power Supply Pins 1.4.2. F-Tile Transceiver Pins
1.5. Agilex™ 7 M-Series R-Tile Pins x
1.5.1. R-Tile Power Supply Pins 1.5.2. R-Tile Transceiver Pins
1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins
1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines x
1.7.1. Example 1— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR4 1.7.2. Example 2— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR5 1.7.3. Example 3— Agilex™ 7 M-Series Devices with R-Tile and F-Tile, Without HBM2E Using DDR4 1.7.4. Example 4— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR4 1.7.5. Example 5— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR5 1.7.6. Example 6— Agilex™ 7 M-Series Devices with F-Tile only and Without HBM2E Using DDR5
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

1.5.1. R-Tile Power Supply Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 15.  R-Tile Power Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCC_HSSI_GXR[L,R] Power

Primary digital supply for all digital signals, specific to R-Tile.

For more information about the supported pins, refer to the device pin-out file.

Connect VCC_HSSI_GXR to a 0.9-V low noise switching regulator. Refer to Agilex™ 7 Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Connect to GND if not used.

VCCH_GXR[L,R] Power

Secondary high-voltage analog supply for transceivers.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCH_GXR to a 1.8-V low noise switching regulator. This voltage rail can be shared with VCCPT using proper isolation filtering.

To minimize regulator switching noise impact on channel jitter performance, keep the regulator switching frequency below 1 MHz. Refer to Agilex™ 7 Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Connect to GND if not used.

VCCED_GXR[L,R] Power

Transceiver digital supply.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCED_GXR to a dedicated 0.9-V linear regulator or low noise switching regulator. You have an option to share the same regulator with VCC_HSSI_GXR. Refer to Agilex™ 7 Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Connect to GND if not used.

VCCRT_GXR[L,R] Power

Analog power, used for the high-speed circuitry for the R-Tile.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCRT_GXR to a dedicated 1.0-V linear regulator or low noise switching regulator. You have an option to share the same regulator with VCCERT_FGT_GXF. Refer to Agilex™ 7 Power Distribution Network Design Guidelines for fitter details and decoupling capacitor requirement.

Connect to GND if not used.

VCCE_DTS_GXR[L,R] Power

DTS reference voltage at 1.0 V.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCE_DTS_GXR to the same regulator as VCCE_PLL_GXR. Refer to Agilex™ 7 Power Distribution Network Design Guidelines for fitter details and decoupling capacitor requirement.

Connect to GND when not used.

VCCE_PLL_GXR[L,R] Power

Power for PLL reference signal.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCE_PLL_GXR to the same regulator as VCCE_DTS_GXR. Refer to Agilex™ 7 Power Distribution Network Design Guidelines for fitter details and decoupling capacitor requirement.

Connect to GND when not used.

VCCHFUSE_GXR[L,R] Power

Power supply for programmable eFuse.

For more information about the supported pins, refer to the device pin-out file.

Share the 1.0-V power rail from group 1.

Connect to GND when the R-Tile transceivers are not used. For more details about the decoupling recommendations for this voltage rail, refer to Agilex™ 7 Power Distribution Network Design Guidelines .

VCCCLK_GXR[L,R] Power

Primary digital supply for all digital signals, specific to R-Tile.

For more information about the supported pins, refer to the device pin-out file.

Share the 1.0-V power rail from group 1.

VCCCLK_GXR can share through ferrite bead. Refer to Agilex™ 7 Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Connect to GND when not used.

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