Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

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ID 776197
Date 6/12/2024
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Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series x
1.1. Pins Status for Agilex™ 7 M-Series Devices 1.2. Agilex™ 7 M-Series FPGA Core Pins 1.3. Agilex™ 7 M-Series HBM2E Pins 1.4. Agilex™ 7 M-Series F-Tile Pins 1.5. Agilex™ 7 M-Series R-Tile Pins 1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins 1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines 1.8. Notes to Agilex™ 7 M-Series Device Family Pin Connection Guidelines 1.9. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1.2. Agilex™ 7 M-Series FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 M-Series HBM2E Pins x
1.3.1. HBM2E Power Supply Pins 1.3.2. HBM2E Signal Pins
1.4. Agilex™ 7 M-Series F-Tile Pins x
1.4.1. F-Tile Power Supply Pins 1.4.2. F-Tile Transceiver Pins
1.5. Agilex™ 7 M-Series R-Tile Pins x
1.5.1. R-Tile Power Supply Pins 1.5.2. R-Tile Transceiver Pins
1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins
1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines x
1.7.1. Example 1— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR4 1.7.2. Example 2— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR5 1.7.3. Example 3— Agilex™ 7 M-Series Devices with R-Tile and F-Tile, Without HBM2E Using DDR4 1.7.4. Example 4— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR4 1.7.5. Example 5— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR5 1.7.6. Example 6— Agilex™ 7 M-Series Devices with F-Tile only and Without HBM2E Using DDR5
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

1.7.1. Example 1— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR4

Table 30.  Power Supply Sharing Guidelines for Agilex™ 7 M-Series Devices with R-Tile, F-Tile Transceivers, and HBM2E, Using DDR4Example Requiring 9 Power Regulators
Power Pin Name Regulator Group Voltage Level (V) Supply Tolerance Power Source Regulator Sharing Notes
VCC 1 SmartVID1, 0.8 ±3% Switcher 2 Share

Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering.

For -4X devices, VCC and VCCP are powered by SmartVID and a separate fixed 0.8 V supply must be used for VCCL_HPS and filtered VCCPLLDIG_HPS.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Agilex™ 7 M-Series device, you must still provide power to these power supply pins. Do not leave the VCCL_HPS and VCCPLLDIG_HPS power supply pins floating or connected to GND.

VCCP
VCCL_HPS
VCCPLLDIG_HPS Filter
VCCH 2 0.8 ±3% Switcher2 Share

Connect these rails to a dedicated 0.8-V power supply.

When implementing a filtered supply topology, you must consider the IR drop across the filter.
VCC_HSSI_GXF
VCCL_SDM
VCCLPLL_NOC Filter
VCCPLLDIG_SDM Filter
VCCPLLDIG_NOC Filter
VCC_HSSI_GXR 3 0.9 ±3% Switcher2 Share Connect VCC_HSSI_GXR, VCCH_SDM, and VCCED_GXR to a dedicated 0.9-V power supply.
VCCH_SDM
VCCED_GXR
VCCERT_FGT_GXF 4

1.0

±2.5%

Switcher2 or Linear

Share

Connect to a dedicated 1.0-V power supply.
VCCERT1_FHT_GXF
VCCERT2_FHT_GXF
VCCRT_GXR
VCCCLK_GXR
VCCFUSEWR_GXF
VCCHFUSE_GXR
VCCFUSECORE_GXF
VCCE_PLL_GXR 5 1.0 ± 2% Linear Share Connect to a dedicated 1.0-V reference source.
VCC_DTS_GXR
VCCEHT_FHT_GXF 6 1.5 -2.5%to +2% Linear Isolate Connect to a dedicated 1.5-V power supply.
VCCPT 7

1.8

 ±3% Switcher2

Share

Connect VCCPT to a dedicated 1.8-V power supply.

Connect VCCADC, VCCPLL_SDM, VCCPLL_HPS, VCCH_FGT_GXF, and VCCCLK_GXF to the same power plane with proper isolation filtering.

Depending on the regulator capabilities, you have the option to share this supply with multiple Agilex™ 7 M-Series devices.

VCCIO_NOC
VCCIO_SDM
VCCIO_HPS
VCCFUSEWR_SDM
VCCH_FGT_GXF Filter
VCCH_GXR Filter
VCCADC Filter
VCCPLL_SDM
VCCPLL_HPS
VCCPLL_NOC Filter
VCCCLK_GXF Filter
VCCM_PUMP_HBM 8 2.5 ±5% Switcher2 Isolate Connect to a dedicated 2.5-V power supply.
VCCRCORE 9 1.2 ±5% or ±3%3 Switcher2 Share

Connect to a dedicated 1.2-V power supply.

When implementing a filtered supply topology, you must consider the IR drop across the filter.
VCCIO_PIO_T/B
VCCIO_PIO_SDM
VCCIO_UIB

Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Agilex™ 7 M-Series devices is provided in the following figure.

Figure 1. Example Power Supply Sharing Guidelines for Agilex™ 7 M-Series Devices with F-Tile, R-Tile, and HBM2E Using DDR4
Related Information
1 For the SmartVID voltage range, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series .
2 When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 4 of the Notes to Agilex™ 7 M-Series Device Family Pin Connection Guidelines .
3 You may supply the VCCIO_PIO voltage rail of a sub-bank with a ±5% voltage tolerance only if the entire sub-bank is operating in any of the LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, or 1.2 V True Differential Signaling input standard, PHY Lite mode, or GPIO mode. Otherwise, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.
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