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1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview
2. M-Series Clocking and PLL Architecture and Features
3. M-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. I/O PLL Reconfiguration Using EMIF Calibration IP
7. Agilex™ 7 Clocking and PLL User Guide: M-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: M-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Clocking Constraints
3.6. IP Core Constraints
3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
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6.3.3. Reconfiguring The I/O PLL
- Set the address bus value for s0_axi4lite_awaddr according to the table below:
Table 17. Reconfiguring The I/O PLL Address Bus Value Value s0_axi4lite_awaddr [7:0] Divide Settings Address s0_axi4lite_awaddr [20:13] I/O PLL Base Address s0_axi4lite_awaddr [23:21] 3’b101 - Set the address bus value for s0_axi4lite_awaddr [7:0] and the data bus value for s0_axi4lite_wdata [31:0] as the desired PLL setting. For more information about Reconfiguration table, refer to the Address Bus and Data Bus Settings.
- Repeat the steps above to set address bus and data bus value for the desired I/O PLL reconfiguration setting.
- Set address bus value of s0_axi4lite_awaddr [7:0] = 0x80, assert data bus value for s0_axi4lite_wdata [2] for 10 ns to reset PLL. Alternatively, you can utilize the reset port in the PLL to implement a 10ns reset.
- After the I/O PLL reconfiguration is complete, you must manually trigger the I/O PLL recalibration.
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