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1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview
2. M-Series Clocking and PLL Architecture and Features
3. M-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. I/O PLL Reconfiguration Using EMIF Calibration IP
7. Agilex™ 7 Clocking and PLL User Guide: M-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: M-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Clocking Constraints
3.6. IP Core Constraints
3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
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2.2.10. PLL Cascading
M-Series devices support PLL-to-PLL cascading. You can cascade a maximum of two PLLs. PLL cascading synthesizes more output clock frequencies than a single PLL.
M-Series devices support the following PLL-to-PLL cascading modes for I/O bank I/O PLL and I/O Bank Fabric-Feeding I/O PLL. UIB fabric-feeding I/O PLL do not support cascading.
- I/O Bank I/O-PLL-to-I/O Bank I/O-PLL cascading
- I/O Bank I/O-PLL-to-I/O Bank fabric-feeding I/O-PLL cascading
- I/O Bank fabric-feeding I/O-PLL-to I/O Bank I/O-PLL cascading
Cascading of PLLs can be done via two paths: via dedicated cascade path or via core clock fabric.
- Cascading via dedicated cascade path—upstream I/O PLL and downstream I/O PLL must be in the same I/O column and are placed adjacently.
- Cascading via core clock fabric—no restriction on locations of upstream and downstream I/O PLL.
The permit_cal input of the downstream I/O PLL must be connected to the locked output of the upstream I/O PLL in both PLL cascading modes.
The following figures show the connectivity required between the upstream and downstream I/O PLL for both the PLL cascading modes.
Figure 17. Cascading Via Dedicated Cascade Path
Figure 18. Cascading Via Core Clock Fabric