Visible to Intel only — GUID: otx1548753832693
Ixiasoft
1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview
2. M-Series Clocking and PLL Architecture and Features
3. M-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. I/O PLL Reconfiguration Using EMIF Calibration IP
7. Agilex™ 7 Clocking and PLL User Guide: M-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: M-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Clocking Constraints
3.6. IP Core Constraints
3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
Visible to Intel only — GUID: otx1548753832693
Ixiasoft
5.2.3. IOPLL IP Core Parameters - Cascading Tab
Parameter | Value | Description |
---|---|---|
Connect to an upstream PLL through Core clock Network Cascading (create a permit_cal input signal) | On or Off | Turn on to create an input port to enable destination (downstream) PLL power-up calibration. Connect source (upstream) PLL locked signal to this input port. |
Connect outclk to a downstream PLL through Core Clock Network Cascading | On or Off | Turn on to configure the PLL as an upstream PLL. Connect (upstream) PLL output clock signal to the refclk port of (downstream) PLL. |
cascade_out source | 5–6 15 | Specifies which output clock to be used as cascading source. |
Create an adjpllin or cclk signal to connect with an upstream PLL | On or Off | Turn on to create an input port, which indicates that this PLL is a destination and connects with a source (upstream) PLL. |
Create a cascade_out signal to connect to a downstream PLL. | On or Off | Turn on to create the cascade_out port, which indicates that this PLL is a source and connects with a destination (downstream) PLL. |
15 When outclk6 is enabled, cascade_out source can only be C6; cascade_out source can be C5 only if outclk6 is not enabled.