Visible to Intel only — GUID: uda1719108952692
Ixiasoft
1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview
2. M-Series Clocking and PLL Architecture and Features
3. M-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. I/O PLL Reconfiguration Using EMIF Calibration IP
7. Agilex™ 7 Clocking and PLL User Guide: M-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: M-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Clocking Constraints
3.6. IP Core Constraints
3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
Visible to Intel only — GUID: uda1719108952692
Ixiasoft
6.4. Axilite Interface Ports in the EMIF Calibration IP
Port Name | Direction | Description |
---|---|---|
s0_axi4lite_awaddr | input | Write Address |
s0_axi4lite_awvalid | input | Write Address Valid |
s0_axi4lite_awready | output | Write Address Ready |
s0_axi4lite_wdata | input | Write Data |
s0_axi4lite_wstrb | input | Write Strobes |
s0_axi4lite_wvalid | input | Write Valid |
s0_axi4lite_wready | output | Write Ready |
s0_axi4lite_bresp | output | Write Response |
s0_axi4lite_bvalid | output | Write Response Valid |
s0_axi4lite_bready | input | Response Ready |
s0_axi4lite_araddr | input | Read Address |
s0_axi4lite_arvalid | input | Read Address Valid |
s0_axi4lite_arready | output | Read Address Ready |
s0_axi4lite_rdata | output | Read Data |
s0_axi4lite_rresp | output | Read Response |
s0_axi4lite_rvalid | output | Read Valid |
s0_axi4lite_rready | input | Read Ready |
s0_axi4lite_awprot | input | Write Protection Type |
s0_axi4lite_arprot | input | Read Protection Type |
s0_axi4lite_clk | input | Axilite clock |
s0_axi4lite_rst_n | input | Axilite reset |
pll_calbus_0 | input | Bus that connects to pll_calbus in the IOPLL Intel FPGA IP core. |
pll_calbus_readdata_0 | output | Bus that connects to pll_calbus_readdata in the IOPLL Intel® FPGA IP core. |