Agilex™ 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 7/25/2024
Public
Document Table of Contents

6. I/O PLL Reconfiguration Using EMIF Calibration IP

You can use M-Series devices to implement phase-locked loop (PLL) reconfiguration and dynamic phase shift for I/O PLLs.

The M-Series I/O PLL supports dynamic reconfiguration when the device is in user mode. With the dynamic reconfiguration feature, you can reconfigure the I/O PLL settings in real time. You can change the divide settings of the PLL through AXI4-Lite interfaces in the EMIF Calibration IP, without the need to reconfigure the entire FPGA. The M-Series I/O PLL uses divide counters (N, M, and C counters) and a voltage-controlled oscillator (VCO) to synthesize the desired phase and frequency output.

You can use the EMIF Calibration IP as follows:

  • I/O PLL Reconfiguration
    • Enable dynamic reconfiguration of PLL using EMIF Calibration IP option from the dynamic reconfiguration tab of the IOPLL Intel® FPGA IP to reconfigure the individual I/O PLL registers. You can perform dynamic phase shift using the EMIF Calibration IP as well.
  • Recalibration of the I/O PLL
    • Perform recalibration of the I/O PLL without any reconfiguration.
    • Trigger recalibration if the reference clock frequency changes.
  • I/O PLL clock gating
    • Gate and un-gate I/O PLL output clock 0 to output clock 6 of the I/O PLL.