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1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview
2. M-Series Clocking and PLL Architecture and Features
3. M-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. I/O PLL Reconfiguration Using EMIF Calibration IP
7. Agilex™ 7 Clocking and PLL User Guide: M-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: M-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Clocking Constraints
3.6. IP Core Constraints
3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
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5.2.2. IOPLL IP Core Parameters - Settings Tab
Parameter | Value | Description |
---|---|---|
PLL Auto Reset | On or Off | Automatically self-resets the PLL on loss of lock. |
Create a second input clk ‘refclk1’ | On or Off | Turn on to provide a backup clock attached to your PLL that can switch with your original reference clock. |
Second Reference Clock Frequency 14 0 | — | Selects the frequency of the second input clock signal. The default value is 100.0 MHz. The minimum and maximum value is dependent on the device used. |
Create an ‘active_clk’ signal to indicate the input clock in use 0 | On or Off | Turn on to create the activeclk output. The activeclk output indicates the input clock which is in use by the PLL. Output signal low indicates refclk and output signal high indicates refclk1. |
Create a ‘clkbad’ signal for each of the input clocks 0 | On or Off | Turn on to create two clkbad outputs, one for each input clock. Output signal low indicates the clock is working and output signal high indicates the clock is not working. |
Switchover Mode 0 | Automatic Switchover, Manual Switchover, or Automatic Switchover with Manual Override | Specifies the switchover mode for design application. The IP supports three switchover modes:
|
Enable access to I/O Bank clock ports | On or Off | This options enables the IOPLL's I/O bank clock ports. The ports are exported instead of outclks, and can be configured through corresponding outclk settings (the outclks that correspond to periphery ports are indicated in the 'Output Clocks' section). The clock ports can be connected to one LVDS only |
Enable access to the PLL DPA output port 0 | On or Off | Turn on to enable the PLL DPA output port. |
Enable access to PLL external clock output port | On or Off | Turn on to enable the PLL external clock output port. |
Specifies which outclk to be used as extclk_out[0] source | C0–C3 (I/O bank) | Specifies the outclk port to be used as extclk_out[0] source. |
Specifies which outclk to be used as extclk_out[1] source | C0–C3 (I/O bank) | Specifies the outclk port to be used as extclk_out[1] source. |
14 This parameter is only available when Create a second input clk 'refclk1' is turned on.