Visible to Intel only — GUID: lxo1719108180799
Ixiasoft
Visible to Intel only — GUID: lxo1719108180799
Ixiasoft
6.2. Implementing I/O PLL Reconfiguration using EMIF Calibration IP
The EMIF Calibration IP is capable of three functional reconfigurations. The data bit setting in s0_axi4lite_awaddr [26:0] determines the reconfiguration operation. During reconfiguration, EMIF Calibration IP reconfigures the individual I/O PLL setting using the AXI4-Lite interfaces. If configuration parameters are set to the illegal configuration settings, I/O PLL may lose the lock, leading to device reliability problems. Altera recommends that you strictly follow the guidelines as follows:
- You must ensure the configuration setting is a legal value so that the I/O PLL has a legal configuration. To ensure your configuration is legal, refer to the IOPLL IP Core Parameters - Advanced Parameters Tab table for the correct configuration settings.
- If the value to be reconfigured makes up only a part of the 32-bit register at the specified address in the I/O PLL’s internal memory, you must perform a read-modify-write operation and ensure that you do not overwrite the remaining bits of the 32-bit register.
- After performing dynamic reconfiguration, the I/O PLL must be recalibrated. You must manually trigger the recalibration of the I/O PLL. Recalibration is not needed for clock gating and dynamic phase shift reconfiguration.