Agilex™ 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 7/25/2024
Public
Document Table of Contents

6.3.5. Clock Gating Using EMIF Calibration IP (Optional)

  1. Set the address bus value for s0_axi4lite_awaddr according to the table below:
    Table 18.  Clock Gating Using EMIF Calibration IP
    Address Bus Value Value
    s0_axi4lite_awaddr [7:0] 0x54
    s0_axi4lite_awaddr [20:13] I/O PLL Base Address
    s0_axi4lite_awaddr [23:21] 3’b101
  2. Set the data bus value for s0_axi4lite_wdata [24:18] accordingly.

    For more information about the Reconfiguration table, refer to the Address Bus and Data Bus Settings.