Agilex™ 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 7/25/2024
Public
Document Table of Contents

6.5.1. Divide Settings and the Corresponding Data Bit Setting for Reconfiguration

Table 20.  Divide Settings and Corresponding Address Bus for Reconfiguration
Divide Settings Write Address Bus Setting

[ 0:7]

Parameter Write Data Bus Setting Description
M Counter

0x40

High Count data[28:20]
  • Total count for M Counter
Bypass Enable 16 data[31]
  • Data[31]=bypass enable
    • Data[31]=1, bypass is enabled. The counter is bypassed with counter division value = 1.
N Counter High Count data[7:0]
  • Data[7:0]=high_count
  • Data[16:9]=low_count
  • total_count=high_count+low_count
Low Count data[16:9]
Odd Division 16 data[17]
  • Data[17]=Odd division
    • Data[17]= 0, odd division is disabled. The selected counter duty cycle = high_count/ total_count.
  • Data[17]= 1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable 16 data[8]
  • Data[8]=bypass enable
    • Data[8]=1, bypass is enabled. The counter is bypassed with counter division value = 1.
C0 0x5C High Count data[7:0]
  • Data[7:0]=high_count
  • Data[30:23]=low_count
  • total_count=high_count+low_count
Low Count data[30:23]
Odd Division16 data[31]
  • Data[31]=Odd division
    • Data[31]= 0, odd division is disabled. The selected counter duty cycle = high_count/ total_count.
  • Data[31]= 1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable16 data[8]
  • Data[8]=bypass enable
    • Data[8]=1, bypass is enabled. The counter is bypassed with counter division value = 1.
Phase Shift data[21:19]
  • Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period.
C1 0x60 High Count data[7:0]
  • Data[7:0]=high_count
  • Data[30:23]=low_count
  • total_count=high_count+low_count
Low Count data[30:23]
Odd Division16 data[31]
  • Data[31]=Odd division
    • Data[31]= 0, odd division is disabled. The selected counter duty cycle = high_count/ total_count.
  • Data[31]= 1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable16 data[8]
  • Data[8]=bypass enable
    • Data[8]=1, bypass is enabled. The counter is bypassed with counter division value = 1.
Phase Shift data[21:19]
  • Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period.
C2 0x64 High Count data[7:0]
  • Data[7:0]=high_count
  • Data[30:23]=low_count
  • total_count=high_count+low_count
Low Count data[30:23]
Odd Division 16 data[31]
  • Data[31]=Odd division
    • Data[31]= 0, odd division is disabled. The selected counter duty cycle = high_count/ total_count.
  • Data[31]= 1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable 16 data[8]
  • Data[8]=bypass enable
    • Data[8]=1, bypass is enabled. The counter is bypassed with counter division value = 1.
Phase Shift data[21:19]
  • Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period.
C3 0x68 High Count data[7:0]
  • Data[7:0]=high_count
  • Data[30:23]=low_count
  • total_count=high_count+low_count
Low Count data[30:23]
Odd Division 16 data[31]
  • Data[31]=Odd division
    • Data[31]= 0, odd division is disabled. The selected counter duty cycle = high_count/ total_count.
  • Data[31]= 1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable16 data[8]
  • Data[8]=bypass enable
    • Data[8]=1, bypass is enabled. The counter is bypassed with counter division value = 1.
Phase Shift data[21:19]
  • Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period.
C4 0x6C High Count data[7:0]
  • Data[7:0]=high_count
  • Data[30:23]=low_count
  • total_count=high_count+low_count
Low Count data[30:23]
Odd Division 16 data[31]
  • Data[31]=Odd division
      • Data[31]= 0, odd division is disabled. The selected counter duty cycle = high_count/ total_count.
  • Data[31]= 1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable16 data[8]
  • Data[8]=bypass enable
    • Data[8]=1, bypass is enabled. The counter is bypassed with counter division value = 1.
Phase Shift data[21:19]
  • Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period.
C5 0x70 High Count data[7:0]
  • Data[7:0]=high_count
  • Data[30:23]=low_count
  • total_count=high_count+low_count
Low Count data[30:23]
Odd Division16 data[31]
  • Data[31]=Odd division
    • Data[31]= 0, odd division is disabled. The selected counter duty cycle = high_count/ total_count.
  • Data[31]= 1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable16 data[8]
  • Data[8]=bypass enable
    • Data[8]=1, bypass is enabled. The counter is bypassed with counter division value = 1.
Phase Shift data[21:19]
  • Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period.
C6 0x74 High Count data[7:0]
  • Data[7:0]=high_count
  • Data[30:23]=low_count
  • total_count=high_count+low_count
Low Count data[30:23]
Odd Division16 data[31]
  • Data[31]=Odd division
      • Data[31]= 0, odd division is disabled. The selected counter duty cycle = high_count/ total_count.
  • Data[31]= 1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable 16 data[8]
  • Data[8]=bypass enable
    • Data[8]=1, bypass is enabled. The counter is bypassed with counter division value = 1.
Phase Shift data[21:19]
  • Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period.
Charge Pump Current 0x44 Charge Pump Settings data[15:1]
  • Data[15:1] = Charge Pump Setting
    • Configure charge pump setting [15:1]

      For more details about Reconfiguration table, refer to the Address and Data Bus Settings.

Calibration 0x88 Calibration Request data[11]
  • Data[11] = Request Calibration
    • Data[11] = 1, to request calibration
16 Perform a read-modify-write operation to configure this setting. PLL may lose lock and can cause reliability issue to your device if you configure with the wrong PLL setting, configure the wrong bit, or overwrite the whole byte for settings that made up just part of one byte.