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1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview
2. M-Series Clocking and PLL Architecture and Features
3. M-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. I/O PLL Reconfiguration Using EMIF Calibration IP
7. Agilex™ 7 Clocking and PLL User Guide: M-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: M-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Clocking Constraints
3.6. IP Core Constraints
3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
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2.2.1. PLL Features
Feature | I/O Bank I/O PLL 2 | Fabric-Feeding I/O PLL2 |
---|---|---|
Integer PLL | Yes | Yes |
Number of C output counter | 4 | 7 |
M counter divide factor range | 4 to 320 | 4 to 320 |
N counter divide factor range | 1 to 110 | 1 to 110 |
C counter divide factor range | 1 to 510 | 1 to 510 |
Dedicated external clock outputs 3 | Yes | — |
Dedicated clock input pins4 5 | Yes | Yes |
External feedback input pin | Yes | — |
Source synchronous compensation 6 0 | Yes | Yes |
Direct compensation | Yes | Yes |
Normal compensation 7 | Yes | Yes |
Zero-delay buffer compensation | Yes | — |
External feedback compensation | Yes | — |
LVDS compensation | Yes | — |
Voltage-controlled oscillator (VCO) output drives the DPA clock | Yes | — |
Phase shift resolution 8 | 39.0626 ps | 39.0626 ps |
Programmable duty cycle | Yes | Yes |
Power down mode | Yes | Yes |
Bandwidth setting9 | — | — |
Spread-spectrum input clock tracking 10 | Yes | Yes |
Spread-Spectrum Clocking Parameter | Setting |
---|---|
Modulation frequency | 200 kHz |
Center or down spread | Down spread |
Frequency deviation | ±1% |
Modulation profile | Triangle |
2 I/O PLL Type is determined by the Intel Quartus Prime software automatically, based on the assigned location of the I/O PLL in Assignment Editor.
3 For dedicated external clock outputs, you must enable access to external clock output port through IOPLL Intel® FPGA IP core. There are 2 dedicated external clock output available for each I/O bank I/O PLL. I/O PLL only supports True Differential Signaling I/O Standard for dedicated external clock outputs.
4 I/O PLL only supports True Differential Signaling I/O Standard for dedicated clock input pins.
5 For Fabric-Feeding I/O PLL located at the UIBSS, the dedicated clock input pins only support 1.2V True Differential Signaling I/O Standard. Ensure that reference clock is stable and free-running at the start of FPGA configuration.
6 Non-dedicated feedback path option is available for this compensation mode.
7 Non-dedicated feedback path option is also available for normal compensation
8 The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the M-Series devices can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.
9 Bandwidth setting is selected by the Intel Quartus Prime software automatically depending on the M counter value.
10 Provided that input clock jitter is within the input jitter tolerance specifications. Intel recommends that the spread-spectrum support profile is down spread, ±0.5% and Fmod = 200 kHz.