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1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview
2. M-Series Clocking and PLL Architecture and Features
3. M-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. I/O PLL Reconfiguration Using EMIF Calibration IP
7. Agilex™ 7 Clocking and PLL User Guide: M-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: M-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Clocking Constraints
3.6. IP Core Constraints
3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
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6.2.1. Setting Up the IOPLL Intel® FPGA IP
Figure 25. IOPLL Intel® FPGA IP
- At the dynamic reconfiguration tab, enable dynamic reconfiguration of PLL using calibration IP.
- Set the respective base address for the I/O PLL desired to be configured from 0 to 255. You cannot share the same base address if you use more than one PLL in the design. For instance, If PLL 1 Base address is assigned to d’20. Then, the next closest address that can be assigned for PLL2 is d’40, and for PLL3 is d’60. Quartus® Prime reads the base address and knows which PLL on the chip to reconfigure.
Note: I/O bank cannot simultaneously support a PLL running dynamic reconfiguration and an EMIF.