Agilex™ 7 Clocking and PLL User Guide: M-Series

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ID 769001
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview 2. M-Series Clocking and PLL Architecture and Features 3. M-Series Clocking and PLL Design Considerations 4. Clock Control Intel® FPGA IP Core 5. IOPLL Intel® FPGA IP Core 6. I/O PLL Reconfiguration Using EMIF Calibration IP 7. Agilex™ 7 Clocking and PLL User Guide: M-Series Archives 8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: M-Series
1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. M-Series Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sectors 2.1.1.3. Programmable Clock Routing
2.1.3. Clock Control Features x
2.1.3.1. Clock Gating 2.1.3.2. Clock Divider
2.1.3.1. Clock Gating x
2.1.3.1.1. Root Clock Gate 2.1.3.1.2. Sector Clock Gate 2.1.3.1.3. I/O PLL Clock Gate 2.1.3.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Locations 2.2.4. PLL Architecture 2.2.5. PLL Control Signals 2.2.6. PLL Feedback Modes 2.2.7. Clock Multiplication and Division 2.2.8. Programmable Phase Shift 2.2.9. Programmable Duty Cycle 2.2.10. PLL Cascading 2.2.11. PLL Input Clock Switchover 2.2.12. PLL Reconfiguration and Dynamic Phase Shift 2.2.13. PLL Calibration
2.2.5. PLL Control Signals x
2.2.5.1. Reset 2.2.5.2. Locked
2.2.6. PLL Feedback Modes x
2.2.6.1. Direct Compensation Mode 2.2.6.2. LVDS Compensation Mode 2.2.6.3. Source Synchronous Compensation Mode 2.2.6.4. Normal Compensation Mode 2.2.6.5. Zero-Delay Buffer Mode 2.2.6.6. External Feedback Mode
2.2.11. PLL Input Clock Switchover x
2.2.11.1. Automatic Switchover 2.2.11.2. Automatic Switchover with Manual Override 2.2.11.3. Manual Clock Switchover
2.2.13. PLL Calibration x
2.2.13.1. Power-Up Calibration 2.2.13.2. User Calibration 2.2.13.3. Static Phase Error Calibration 2.2.13.4. Output Clock Duty Cycle Correction
3. M-Series Clocking and PLL Design Considerations x
3.1. Guidelines: Clock Switchover 3.2. Guidelines: Timing Closure 3.3. Guidelines: Resetting the PLL 3.4. Guidelines: Configuration Constraints 3.5. Clocking Constraints 3.6. IP Core Constraints 3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
4. Clock Control Intel® FPGA IP Core x
4.1. Release Information for Clock Control Intel® FPGA IP 4.2. Clock Control Intel® FPGA IP Core Parameters 4.3. Clock Control Intel® FPGA IP Core Ports and Signals
5. IOPLL Intel® FPGA IP Core x
5.1. Release Information for IOPLL Intel® FPGA IP 5.2. IOPLL IP Core Parameters 5.3. IOPLL IP Core Ports and Signals
5.2. IOPLL IP Core Parameters x
5.2.1. IOPLL IP Core Parameters - PLL Tab 5.2.2. IOPLL IP Core Parameters - Settings Tab 5.2.3. IOPLL IP Core Parameters - Cascading Tab 5.2.4. IOPLL IP Core Parameters - Advanced Parameters Tab
6. I/O PLL Reconfiguration Using EMIF Calibration IP x
6.1. Release Information for EMIF Calibration IP 6.2. Implementing I/O PLL Reconfiguration using EMIF Calibration IP 6.3. Reconfiguration Through EMIF Calibration IP 6.4. Axilite Interface Ports in the EMIF Calibration IP 6.5. Address Bus and Data Bus Settings
6.2. Implementing I/O PLL Reconfiguration using EMIF Calibration IP x
6.2.1. Setting Up the IOPLL Intel® FPGA IP 6.2.2. Setting Up the EMIF Calibration IP 6.2.3. Connectivity Between IOPLL and EMIF Calibration IP
6.3. Reconfiguration Through EMIF Calibration IP x
6.3.1. Enabling Reconfiguration for The Desired I/O PLL 6.3.2. Clearing off Calibration Statuses 6.3.3. Reconfiguring The I/O PLL 6.3.4. Recalibration Using EMIF Calibration IP 6.3.5. Clock Gating Using EMIF Calibration IP (Optional)
6.5. Address Bus and Data Bus Settings x
6.5.1. Divide Settings and the Corresponding Data Bit Setting for Reconfiguration 6.5.2. Data Bus Setting for Clock Gating Reconfiguration 6.5.3. Data Bus Setting For Charge Pump Current
1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview
2. M-Series Clocking and PLL Architecture and Features
3. M-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. I/O PLL Reconfiguration Using EMIF Calibration IP
7. Agilex™ 7 Clocking and PLL User Guide: M-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: M-Series

4.3. Clock Control Intel® FPGA IP Core Ports and Signals

Table 6.   Clock Control Intel® FPGA IP Core Ports for M-Series Devices
Port Name Description
inclk Input signal to the clock network.
inclk0x, inclk1x, inclk2x, inclk3x Input signals to the clock network based on the value selected for the Number of Clock Inputs parameter.
clkselect[]

Input that dynamically selects the clock source to drive the clock network that is driven by the clock buffer.

Input port [1 DOWNTO 0] wide.

The following list shows the signal selection for the clkselect[] value:

  • 2’b00 selects inclk0x
  • 2’b01 selects inclk1x
  • 2’b10 selects inclk2x
  • 2’b11 selects inclk3x
outclk Output of the Clock Control Intel® FPGA IP core when Clock Divider option is not selected.
ena Clock enable of the clock gate block. This signal is active-high.
clock_div1x, clock_div2x, clock_div4x Outputs of the Clock Control Intel® FPGA IP core when the Clock Divider option is selected. The exact combination of ports exposed depends on the value specified for the Clock Divider Output Ports parameter.
  • clock_div1x is the same as inclk
  • clock_div2x divides inclk by 2
  • clock_div4x divides inclk by 4
Level Two Title