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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Embedded Processor Design Handbook Archives
9. Document Revision History for the Nios® V Embedded Processor Design Handbook
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios V Processor Booting from On-Chip Memory (OCRAM)
4.7. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.4.1. Prerequisites
6.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.4.3. Creating Nios V Processor Software
6.4.4. Generating Memory Initialization File
6.4.5. Generating System Simulation Files
6.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
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1.2. Intel® Quartus® Prime Software Support
Intel® Quartus® Prime Standard Edition software has the same features as Intel® Quartus® Prime Pro Edition software with exception on features below:
- Provide the SOPCINFO file (.sopcinfo) to the --qsys argument when creating the Board Support Package (BSP).
- Run the niosv-bsp-editor command to invoke the Board Support Package Editor GUI.
- Utilize the following tools to generate the example design:
Tools Steps Graphical User Interface - Search for Nios V/m Processor Intel FPGA IP in IP Catalog.
- Click Add and create a dummy Platform Designer system.
- Select one of the available options.
Command Line Interface - Enter the following command to generate a Nios® V Processor Example Design from Platform Designer:
ip-generate --component-name=intel_niosv_m --file-set=<design name>
Linux*:<quartus_install>/quartus/sopc_builder/bin/ip-generate
Windows*:<quartus_install>\quartus\sopc_builder\bin\ip-generate.exe
- The following are the available design names:
- hello_world_example_design
- gsfi_bootloader_example_design
- uc_tcp_ip_iperf_example_design
- uc_tcp_ip_sss_example_design
Note: Refer to Figure: IP Parameter Editor for Nios V/m Processor Intel FPGA IP.
- The following are the available design names:
Table 1. Nios® V Processor Device Support Nios® V Processor Intel® Quartus® Prime Standard Edition Intel® Quartus® Prime Pro Edition Software version 22.1 22.3 IP version 1.0.0 22.3.0 Device support - Control-block based device
- Intel® MAX® 10
- Intel® Cyclone® IV E
- Intel® Cyclone® IV GX
- Intel® Cyclone® V
- Intel® Cyclone® 10 LP
- Intel® Arria® 10
- Intel® Arria® II GX
- Intel® Arria® II GZ
- Intel® Arria® V
- Intel® Arria® V GZ
- Intel® Stratix® IV
- Intel® Stratix® V
- Control-block based device
- Intel® Cyclone® 10 GX
- Intel® Arria® 10
- SDM-based device
- Intel® Stratix® 10
- Intel® Agilex™
Documentation Refer to the Related Information. Refer to the latest documentations according to the Intel® Quartus® Prime Pro Edition software and IP version.