Nios® V Embedded Processor Design Handbook

Download PDF
ID 726952
Date 10/31/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Nios® V Embedded Processor 2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer 3. Nios® V Processor Software System Design 4. Nios® V Processor Configuration and Booting Solutions 5. Nios® V Processor - Using the MicroC/TCP-IP Stack 6. Nios® V Processor Debugging, Verifying, and Simulating 7. Nios® V Processor — Remote System Update 8. Nios® V Embedded Processor Design Handbook Archives 9. Document Revision History for the Nios® V Embedded Processor Design Handbook
1. About the Nios® V Embedded Processor x
1.1. Intel® FPGA and Embedded Processors Overview 1.2. Intel® Quartus® Prime Software Support 1.3. Embedded System Design 1.4. Nios® V Processor Quick Start Guide
1.4. Nios® V Processor Quick Start Guide x
1.4.1. System Requirements 1.4.2. Nios® V/m Processor Example Design 1.4.3. Software Design Flow 1.4.4. Programming Nios® V/m into the FPGA Device
1.4.1. System Requirements x
1.4.1.1. Hardware and Software Requirements
1.4.2. Nios® V/m Processor Example Design x
1.4.2.1. Generating the Example Design Through Graphical User Interface 1.4.2.2. Generating the Nios® V/m Processor Example Design Using the Command-Line Interface
1.4.2.1. Generating the Example Design Through Graphical User Interface x
1.4.2.1.1. Generating the Nios® V/m Processor Example Design in Platform Designer 1.4.2.1.2. Generating the Nios® V/m Processor Example Design System in Platform Designer
1.4.3. Software Design Flow x
1.4.3.1. Generating the Board Support Package 1.4.3.2. Generating the Application Project File 1.4.3.3. Building the Application Project
1.4.3.1. Generating the Board Support Package x
1.4.3.1.1. Generating the Board Support Package using the BSP Editor GUI 1.4.3.1.2. Generating the Board Support Package using the Command-Line Interface
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer x
2.1. Creating Nios® V Processor System Design with Platform Designer 2.2. Integrating Platform Designer System into the Intel® Quartus® Prime Project 2.3. Designing a Nios® V Processor Memory System 2.4. Clocks and Resets Best Practices 2.5. Assigning a Default Agent
2.1. Creating Nios® V Processor System Design with Platform Designer x
2.1.1. Instantiating Nios® V/m Processor IP Core 2.1.2. Defining System Component Design 2.1.3. Specifying Base Addresses and Interrupt Request Priorities
2.1.1. Instantiating Nios® V/m Processor IP Core x
2.1.1.1. Configure Nios® V Processor Parameters 2.1.1.2. Generate Nios® V processor example design from Platform Designer
2.1.1.1. Configure Nios® V Processor Parameters x
2.1.1.1.1. Debug Tab 2.1.1.1.2. Use Reset Request Tab 2.1.1.1.3. Vectors Tab
2.2. Integrating Platform Designer System into the Intel® Quartus® Prime Project x
2.2.1. Instantiating the Nios® V Processor System Module in the Intel® Quartus® Prime Project 2.2.2. Connecting Signals and Assigning Physical Pin Locations 2.2.3. Constraining the Intel FPGA Design
2.3. Designing a Nios® V Processor Memory System x
2.3.1. Volatile Memory 2.3.2. Non-Volatile Memory 2.3.3. On-Chip Memory Configuration – RAM or ROM
2.4. Clocks and Resets Best Practices x
2.4.1. Reset Request Interface
2.4.1. Reset Request Interface x
2.4.1.1. Typical Use Cases
3. Nios® V Processor Software System Design x
3.1. Nios V Processor Software Development Flow 3.2. Intel FPGA Embedded Development Tools
3.1. Nios V Processor Software Development Flow x
3.1.1. Board Support Package Project 3.1.2. Application Project
3.2. Intel FPGA Embedded Development Tools x
3.2.1. Nios V Board Support Package Editor 3.2.2. RiscFree* IDE for Intel FPGAs 3.2.3. Eclipse CDT for Embedded C/C++ Developer 3.2.4. Nios V Utilities Tools 3.2.5. File Format Conversion Tools 3.2.6. Other Utilities Tools
4. Nios® V Processor Configuration and Booting Solutions x
4.1. Introduction 4.2. Linking Applications 4.3. Nios® V Processor Booting Methods 4.4. Introduction to Nios® V Processor Booting Methods 4.5. Nios® V Processor Booting from Configuration QSPI Flash 4.6. Nios V Processor Booting from On-Chip Memory (OCRAM) 4.7. Summary of Nios® V Processor Vector Configuration and BSP Settings
4.2. Linking Applications x
4.2.1. Linking Behaviour
4.2.1. Linking Behaviour x
4.2.1.1. Default BSP Linking 4.2.1.2. Configurable BSP Linking
4.4. Introduction to Nios® V Processor Booting Methods x
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash 4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier 4.4.3. Nios® V Processor Application Execute-In-Place from OCRAM
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash x
4.4.1.1. alt_load()
4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier x
4.4.2.1. GSFI Bootloader 4.4.2.2. SDM Bootloader
4.5. Nios® V Processor Booting from Configuration QSPI Flash x
4.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) 4.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
4.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) x
4.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash 4.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader) 4.5.1.3. GSFI Bootloader Example Design
4.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash x
4.5.1.1.1. Hardware Design Flow 4.5.1.1.2. Software Design Flow 4.5.1.1.3. Programming Files Generation 4.5.1.1.4. QSPI Flash Programming
4.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader) x
4.5.1.2.1. Hardware Design Flow 4.5.1.2.2. Software Design Flow 4.5.1.2.3. Programming Files Generation 4.5.1.2.4. QSPI Flash Programming
4.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices) x
4.5.2.1. Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader) 4.5.2.2. SDM Bootloader Example Design
4.5.2.1. Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader) x
4.5.2.1.1. Hardware Design Flow 4.5.2.1.2. Software Design Flow 4.5.2.1.3. Software Design Flow (SDM Bootloader Project) Creating the SDM Bootloader BSP Project Configuring BSP Editor and Generating the BSP Project Create the SDM Bootloader Application Project Building the SDM Bootloader Project Generating the HEX File and Initializing the Memory 4.5.2.1.4. Software Design Flow (User Application Project) 4.5.2.1.5. Programming Files Generation 4.5.2.1.6. QSPI Flash Programming SDM
4.6. Nios V Processor Booting from On-Chip Memory (OCRAM) x
4.6.1. Nios V Processor Application Executes in-place from OCRAM
4.6.1. Nios V Processor Application Executes in-place from OCRAM x
4.6.1.1. Hardware Design Flow 4.6.1.2. Software Design Flow 4.6.1.3. Programming
5. Nios® V Processor - Using the MicroC/TCP-IP Stack x
5.1. Introduction 5.2. Software Architecture 5.3. Support and Licensing 5.4. MicroC/TCP-IP Example Designs 5.5. Development Flow 5.6. Operating the Example Designs 5.7. Optional Configuration 5.8. MicroC/TCP-IP Simple Socket Server Concepts
5.4. MicroC/TCP-IP Example Designs x
5.4.1. Hardware and Software Requirements 5.4.2. Overview 5.4.3. Acquiring the Example Design Files 5.4.4. Hardware Design Files 5.4.5. Software Design Files
5.4.5. Software Design Files x
5.4.5.1. MicroC/TCP-IP IPerf Example Design 5.4.5.2. MicroC/TCP-IP Simple Socket Server Example Design
5.5. Development Flow x
5.5.1. Hardware Development Flow 5.5.2. Software Development Flow 5.5.3. Device Programming
5.5.2. Software Development Flow x
5.5.2.1. Creating a BSP project 5.5.2.2. Configuring the BSP 5.5.2.3. Creating an Application Project 5.5.2.4. Building the Application Project 5.5.2.5. HEX File Generation
5.6. Operating the Example Designs x
5.6.1. Operating the MicroC/TCP-IP IPerf 5.6.2. Operating the MicroC/TCP-IP Simple Socket Server
5.7. Optional Configuration x
5.7.1. Configuring Hardware Name 5.7.2. Configuring MAC and IP Addresses 5.7.3. Configuring MicroC/TCP-IP Initialization 5.7.4. Configuring iPerf Server Auto-Initialization
5.7.3. Configuring MicroC/TCP-IP Initialization x
5.7.3.1. Network Task Configuration 5.7.3.2. Network Interface Configuration
5.8. MicroC/TCP-IP Simple Socket Server Concepts x
5.8.1. MicroC/OS-II Resources 5.8.2. Error Handling 5.8.3. MicroC/TCP-IP Stack Default Configuration
6. Nios® V Processor Debugging, Verifying, and Simulating x
6.1. Debugging Nios® V Processor Software Designs 6.2. Debugging Tools 6.3. Additional Embedded Design Considerations 6.4. Simulating Nios® V Processor Designs
6.1. Debugging Nios® V Processor Software Designs x
6.1.1. OpenOCD and Eclipse Embedded CDT 6.1.2. Objdump File 6.1.3. Show Make Commands
6.3. Additional Embedded Design Considerations x
6.3.1. JTAG Signal Integrity 6.3.2. Additional Memory Space for System Prototyping
6.4. Simulating Nios® V Processor Designs x
6.4.1. Prerequisites 6.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer 6.4.3. Creating Nios V Processor Software 6.4.4. Generating Memory Initialization File 6.4.5. Generating System Simulation Files 6.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
6.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer x
6.4.2.1. Using IP and Platform Designer Simulation Setup Scripts
6.4.3. Creating Nios V Processor Software x
6.4.3.1. Generating the Board Support Package 6.4.3.2. Generating the Application Project File 6.4.3.3. Building the Application Project
7. Nios® V Processor — Remote System Update x
7.1. Overview 7.2. Intel® Quartus® Prime Pro Edition Software and Tool Support
7.2. Intel® Quartus® Prime Pro Edition Software and Tool Support x
7.2.1. Intel® Quartus® Prime Pro Edition Software 7.2.2. Programming File Generator
7.2.1. Intel® Quartus® Prime Pro Edition Software x
7.2.1.1. Setting Max Retry Parameter 7.2.1.2. Selecting Factory Load Pin
7.2.2. Programming File Generator x
7.2.2.1. Programming File Generator File Types 7.2.2.2. Bitswap Option 7.2.2.3. Intel® Quartus® Prime Programmer 7.2.2.4. Supported QSPI Flash Devices
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Embedded Processor Design Handbook Archives
9. Document Revision History for the Nios® V Embedded Processor Design Handbook

4.5.2.1.3. Software Design Flow (SDM Bootloader Project)

This section provides the design flow to generate and build the SDM Bootloader project.

Creating the SDM Bootloader BSP Project

To launch the BSP Editor, follow these steps:

  1. In the Platform Designer window, select File > New BSP. The Create New BSP windows appears.
  2. For BSP setting file, navigate to the software/mailbox_bootloader/bsp folder and name the BSP as settings.bsp.

    BSP path: <project directory>/software/mailbox_bootloader/bsp/settings.bsp

  3. For System file (qsys or sopcinfo), select the Nios V/m processor Platform Designer system (.qsys) file.
  4. For Quartus project, select the Quartus Project File.
  5. For Revision, select the correct revision.
  6. For CPU name, select the Nios V/m processor.
  7. Select the Operating system as Altera HAL.
  8. Click Create to create the BSP file.
Figure 54. Create New BSP Window

Configuring BSP Editor and Generating the BSP Project

  1. Go to BSP Editor > Main > Settings
  2. Configure the settings per the following table:
    Table 17.  Settings for BSP Editor
    Settings Action

    hal.max_file_descriptors 5

    		Input as 4

    hal.log_port 5

    		Select as None

    hal.enable_exit 5

    hal.enable_clean_exit 5

    hal.c_plus_plus 5

    		Unchecked to disable the feature.

    hal.sys_clk_timer 5

    hal.timerstamp_timer 5

    hal.stdin 5

    hal.stdout 5

    hal.stderr 5

    		Select as None
    hal.linker

    Enable the following settings:

    • allow_code_at_reset

    • enable_alt_load

    • enable_alt_load_copy_rodata

    • enable_alt_load_copy_rwdata

    • enable_alt_load_copy_exceptions

    hal.make.cflags_user_flags 5

    		Input as -ffunction-sections -fdata-sections

    hal.make.link_flags 5

    		Input as -Wl,--gc-sections

    hal.make.cflags_optimization 5

    		Input as -Os
    :
    Figure 55. hal Settings
    Figure 56. hal.linker Settings
    Figure 57. hal.toolchain Settings
    Figure 58. hal.make Settings
  3. Go to BSP Software Package and enable altera_safeclib
    Figure 59. BSP Software Package
  4. Click the BSP Linker Script tab in the BSP Editor.
  5. Set the .text item in the Linker Section Name to the Bootloader ROM in the Linker Region Name. Set the rest of the items in the Linker Section Name list to the Bootloader RAM.
    Figure 60. Linker Region Settings
  6. Navigate to the BSP Driver tab and disable all drivers (except the Nios V Processor and Mailbox Client Intel FPGA IP).
    Figure 61. BSP Driver tab
  7. Click Generate BSP. Make sure the BSP generation is successful.
  8. Close the BSP Editor.

Create the SDM Bootloader Application Project

  1. Generate the example design files (Refer to SDM Bootloader Example Design). You do not need to build the example design.
  2. Navigate to the software/mailbox_bootloader/app folder in the SDM Bootloader Example Design project.
  3. Copy the SDM bootloader (mailbox_bootloader.c) into the software/mailbox_bootloader/app folder in your project.
  4. Redefine the PAYLOAD_OFFSET in mailbox_bootloader.c.
    Note: The SOF image size influences the PAYLOAD_OFFSET. The PAYLOAD_OFFSET is the start address of the Nios® V application HEX file in QSPI flash and must point to a location after the SOF image. You can determine the minimum PAYLOAD_OFFSET by using the configuration bitstream size from the device datasheet.

    For example, the estimated compressed configuration bitstream size for Intel Stratix 10 SX 2800 is 577 Mbits (72.125 MBytes). The actual size can be equal or smaller than this bitstream size. If the SOF image starts at address 0x0, the SOF image should reached until address 0x44C8FFF (0x44C8A48). With that, the minimum PAYLOAD_OFFSET you can select is 0x4500000.

  5. Launch the Nios V Command Shell.
  6. Execute the command below to generate the SDM bootloader application CMakeLists.txt. 
    niosv-app --app-dir=software/mailbox_bootloader/app\
        --bsp-dir=software/mailbox_bootloader/bsp\
        --srcs=software/mailbox_bootloader/app/mailbox_bootloader.c

Building the SDM Bootloader Project

You can choose to build the SDM bootloader project using the RiscFree* IDE for Intel FPGAs, Eclipse Embedded CDT, or through the command line interface (CLI).

With the CLI , you can build the SDM bootloader using the following commands:

cmake -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Release -B \
        software/mailbox_bootloader/app/release -S \ 
        software/mailbox_bootloader/app

make -C software/mailbox_bootloader/app/release

The SDM bootloader (.elf) file is created in

software/mailbox_bootloader/app/release folder.

Generating the HEX File and Initializing the Memory

A HEX file must be generated from the ELF file so that the HEX file can be used for memory initialization.

  1. Launch the Nios V Command Shell.
  2. For SDM bootloader, use the following command line to convert the ELF to HEX. This command creates the SDM bootloader (bootcopier_rom.hex) file. 
elf2hex software/mailbox_bootloader/app/release/app.elf \
  -o bootcopier_rom.hex -b <base address of Bootloader ROM> \
  -w <data width of Bootloader ROM> -e <end address of Bootloader ROM> -r 4

Recompile the hardware design to memory-initialize the bootcopier_rom.hex into the Bootloader ROM.

Related Information
5 Intel recommends you to use these settings to reduce the SDM bootloader code footprint.
Level Two Title