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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Embedded Processor Design Handbook Archives
9. Document Revision History for the Nios® V Embedded Processor Design Handbook
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios V Processor Booting from On-Chip Memory (OCRAM)
4.7. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.4.1. Prerequisites
6.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.4.3. Creating Nios V Processor Software
6.4.4. Generating Memory Initialization File
6.4.5. Generating System Simulation Files
6.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
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1.4.2. Nios® V/m Processor Example Design
The example design is a “Hello World” program. The complete system is built using the IP blocks in the following table and shown in the following figure:
Components | Description |
---|---|
Nios® V/m Processor Intel® FPGA IP | Runs application by executing instructions. |
JTAG UART Intel® FPGA IP | Enables serial character communication between Nios® V/m processor and host computer. |
On-Chip Memory Intel® FPGA IP | Stores data and instructions. |
Figure 1. Nios® V/m Example Design Block Diagram
Before building and running an application on Nios® V/m processor, you must compile and configure the correct hardware design on the FPGA. The example design provided was configured to run on the Intel Arria® 10 SoC Development Kit.
Note: You can modify the provided design to target your desired board by configuring the target device setting in the provided top.qsf and create_qsys.tcl file, and clock pin setting in the top.qsf file. For more information, refer to Generating the Nios V/m Processor Example Design System in Platform Designer.