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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Embedded Processor Design Handbook Archives
9. Document Revision History for the Nios® V Embedded Processor Design Handbook
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios V Processor Booting from On-Chip Memory (OCRAM)
4.7. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.4.1. Prerequisites
6.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.4.3. Creating Nios V Processor Software
6.4.4. Generating Memory Initialization File
6.4.5. Generating System Simulation Files
6.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
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5.5.1. Hardware Development Flow
You can create the µC/TCP-IP example designs hardware system using the Platform Designer.
- In the Platform Designer, create a new Platform Designer system (sys.qsys).
- Navigate to View > System Scripting.
- Under the Project Scripts, add and run qsys_script_create_system.tcl.
Figure 85. System Scripting Windows
- The generated Platform Designer system consist of the Nios V/m processor, TSE IP, mSGDMA IP and other peripherals. Refer to Hardware Design Files for the complete system.
- Click Generate HDL to generate the system HDL.
- Click Processing > Start Compilation to perform a full hardware compilation and generate the hardware .sof file.
Note: Currently, the hardware .sof file is not memory-initialized with the µC/TCP-IP application. Refer to the following section for more information.