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Visible to Intel only — GUID: izi1638888032251
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4.5.1.3. GSFI Bootloader Example Design
You can generate the GSFI Bootloader Example Design from the IP Catalog. The example design is based on the Intel Arria 10 SoC Development Kit. Using the provided scripts, the hardware and software design are generated, and programmed respectively as SRAM Object Files (.sof) and JTAG Indirect Configuration Files (.jic) into the device.
Use the following steps to generate the GSFI Bootloader Example Design using Platform Designer,
- In the Intel® Quartus® Prime software, go to Tools > Platform Designer.
- In the Platform Designer, select IP Variant.
- For Quartus project, select None.
- In the IP Variant dialog box, specify any name for your IP.
Note: Saving the IP is not required.
- Click Select in the Component type.
- The IP Catalog opens.
- Search for Nios V/m Processor Intel FPGA IP.
- Create the IP design.
Figure 44. IP Parameter Editor for Nios® V/m Processor Intel® FPGA IP
- Click Example Design: “GSFI Bootloader Example Design” and select your project folder.
- Close the IP Parameter Editor. When prompted with Save changes?, you do not need to save the IP. Click Don’t Save.
- Unzip the example design to your project folder. Refer to Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader) Figure and File Description (GSFI Bootloader Example Design) Table for the example design files and the description.
<Intel Quartus Prime installation directory>/niosv/bin/niosv-shell
ip-deploy --component-name=intel_niosv_m --output-name=niosv_m.ip
qsys-generate niosv_m.ip --example_design=niosv_m.gsfi_bootloader_example_design
unzip a10soc_niosv_m_gsfi_bootloader_example_design.zip
File | Description |
---|---|
software/app | Folder containing source code for software application. |
bsp_script.tcl | TCL script to configure the BSP Editor. |
create_design.py | Python script to build the example design and program the device. |
flash_image.cof | Provide information to generate the JIC file using Convert Programming File tool. |
qsys_system_script.tcl | TCL script to generate the example design .qsys file. |
readme.txt | Description and steps to build the example design. |
toggle_issp.tcl | TCL script to reset the design via In-System Sources and Probes (ISSP). |
top.sdc | Example design Synopsys* Design Constraints (.sdc) file. |
top.tcl | TCL script to generate the example design .qpf file and .qsf file. |
top.v | Top-level Verilog design. |
Running the GSFI Bootloader Example Design
- Launch the Nios V Command Shell.
- Run create_design.py to build the example design and program the Intel Arria 10 SoC development kit.
quartus_py create_design.py
- Reset the Nios V processor.
quartus_stp -t toggle_issp.tcl
- Run JUART terminal to view the outputs.
juart-terminal
- In the beginning, the window displays the following message:
- Reaching the end, the window displays the following message: