Nios® V Embedded Processor Design Handbook

ID 726952
Date 10/31/2022
Public

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Document Table of Contents

4.5.1.1.2. Software Design Flow

This section provides the design flow to generate and build a Nios® V processor software project. To ensure a streamlined build flow, you are encouraged to create a similar directory tree in your design project. The software design flow is based on this directory tree.

Use the following steps to create the software project directory tree:

  1. In your design project folder, create a folder called software.
  2. In the software folder, create two folders called app and bsp.
    Figure 23. Software Project Directory Tree

Creating the BSP Project Application

You must edit the BSP editor settings according to the selected Nios® V processor boot options.

To launch the BSP Editor, perform the following steps:

  1. In the Platform Designer window, select File > New BSP. The Create New BSP windows appears.
  2. For BSP setting file, navigate to the software/bsp folder and name the BSP as settings.bsp.

BSP path: <project directory>/software/bsp/settings.bsp

  1. For System file (qsys or sopcinfo), select the Nios V/m processor Platform Designer system (*.qsys).
  2. For Quartus project, select the Quartus Project File.
  3. For Revision, select the correct revision.
  4. For CPU name, select the Nios V/m processor.
  5. Select the Operating system as Altera HAL.
  6. Click Create to create the BSP file.
Figure 24. Create New BSP window

Configuring BSP Editor and Generating the BSP Project

  1. In the BSP Editor, click BSP Linker Script.
  2. In the Linker Section Name perform the following settings:
    1. Set .text to the QSPI flash in the Linker Region Name.
    2. Set .exceptions to OCRAM/ External RAM or QSPI Flash according to your design preference.
    3. Set the rest of the items to the OCRAM or external RAM.
    Figure 25. Linker Region Settings When Exceptions is set to OCRAM/ External RAM
    Figure 26. Linker Region Settings When Exceptions is set to QSPI Flash
  3. Go to Main > Settings > Advanced > hal.linker.
  4. If exception is set to OCRAM or External RAM, enable the following:
    • allow_code_at_reset
    • enable_alt_load
    • enable_alt_load_copy_rodata
    • enable_alt_load_copy_rwdata
    • enable_alt_load_copy_exceptions
    Figure 27. hal.linker Settings for Exception Agent OCRAM or External RAM
  5. If exception is set to QSPI flash, enable the following:
    • allow_code_at_reset
    • enable_alt_load
    • enable_alt_load_copy_rodata
    • enable_alt_load_copy_rwdata
    Figure 28. hal.linker Settings for QSPI Flash
  6. Click Generate BSP. Make sure the BSP generation is successful.
  7. Close the BSP Editor.

Generating the Application Project File

  1. Navigate to the software/app folder and create your Nios® V application source code.
  2. Launch the Nios V Command Shell.
  3. Execute the command below to generate the application CMakeLists.txt.
niosv-app --app-dir=software/app --bsp-dir=software/bsp \
  --srcs=software/app/<Nios V application source code>

Building the Application Project

You can choose to build the application project using the RiscFree* IDE for Intel FPGAs, Eclipse Embedded CDT or through the command line interface (CLI).

If you prefer using CLI, you can build the application using the following command:

cmake -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug -B \
  software/app/debug -S software/app 
 make -C software/app/debug

The application (.elf) file is created in software/app/debug folder.

Generating HEX File

You must generate a .hex file from your application .elf file, so you can create a .jic file suitable for programming flash devices.

  1. Launch the Nios V Command Shell.
  2. For Nios® V processor application execute-in-place (XIP) from configuration QSPI flash, use the following commands line to convert the ELF to HEX for your application. The commands create the application (.hex) file.
elf2flash --input software/app/debug/<Nios V application>.elf \
  --output flash.srec --reset <reset offset + base address of GSFI AVL MEM> \
  --base <base address of GSFI AVL MEM> \
  --end <end address of GSFI AVL MEM>
riscv32-unknown-elf-objcopy --input-target srec --output-target ihex \
  flash.srec <Nios V application>.hex