F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023
Public

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4.6.1. Selecting the Nios® Data Memory Size

The Intel® Quartus® Prime software generates a combined .mif file during the Support Logic Generation step. This file contains the relevant reconfiguration data for all the profiles used in your design on a per-tile basis. Each F-tile in your project generates it's own combined .mif file. This .mif file is located in the <project_directory>/support_logic/ directory. You can determine the required size for the Nios® data memory for your tile by examining a message generated during the Support Logic Generation step. You can find this message in the Message pane of the Intel® Quartus® Prime GUI or in the <project_name>.tlg.rpt file located in the main project directory.

The message contains the exact size of the .mif file required to implement your design and follows the format shown below:

Info(23089): NIOS data memory size 27428 Bytes is needed to store the data for Dynamic Reconfiguration Controller IP dphy_f_hw/dr_dut/dr_f_0

Since this message indicates the minimum Nios® data memory size, you must select a value in the Dynamic Reconfiguration Suite IP's Nios® data memory size pull-down menu which is greater than or equal to the size indicated in the message. Note that the message indicates the size in bytes, whereas the pull-down selections are in Kbytes.

If you do not correctly size your Nios® memory, the Intel® Quartus® Prime software generates an error message such as the following during the Support Logic Generation step.

Error(23051): NIOS data memory size 16K Bytes of Dynamic Reconfiguration Controller IP dphy_f_hw/dr_dut/dr_f_0 is smaller than required MIF Size of 27428Bytes to store the data in NIOS Memory