F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Using QSF-driven Flow 4.4. Dynamic Reconfiguration Rules 4.5. Hardware States and Configuration Profiles 4.6. Nios® -Based Dynamic Reconfiguration Flow 4.7. Using the Tile Assignment Editor 4.8. Visualizing Dynamic Reconfiguration Group Placement 4.9. Assigning IP_COLOCATE Hierarchy 4.10. Example: Dynamic Reconfiguration with Multirate IP Flow 4.11. Example: Dynamic Reconfiguration Programming Sequence 4.12. Dynamic Reconfiguration Error Recovery Handling 4.13. Determining Profile Numbers 4.14. Master Clock Channel 4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment
4.6. Nios® -Based Dynamic Reconfiguration Flow x
4.6.1. Selecting the Nios® Data Memory Size
4.7. Using the Tile Assignment Editor x
4.7.1. Creating .qsf Assignments 4.7.2. Generating the IP_Colocate QSF Assignment
4.14. Master Clock Channel x
4.14.1. Selecting the Master Clock Channel 4.14.2. Automation for selecting the Master Clock Channel
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm 6.33. Dynamic Reconfiguration Local Error Status
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

4.12. Dynamic Reconfiguration Error Recovery Handling

The Recovery enabled option in the Dynamic Reconfiguration Suite GUI allows you to easily recover from an error condition which you might encounter during the dynamic reconfiguration process.

By default, the Recovery enabled parameter is set to Yes. If you are concerned about the size of your combined .mif file, set to No and do not use this feature. Setting this parameter to No reduces the size of your combined .mif file.

If the DR firmware terminates with an error with this feature enabled, it allows you to recover and restore the protocol IP from any state back to the startup profile for the corresponding "Supreme Parent Group". In order to accomplish this restoration, you must set the dyn_rcfg_dr_next_profile_0_reg[17] to 1'b1 and provide any profile ID along with it from the corresponding "Supreme Parent Group" as well as re-trigger the DR process. The Dynamic Reconfiguration Suite IP restores the protocol IP back to the startup profile for the corresponding “Supreme Parent Group”.

The figure below shows an example of the .mif content that highlights the "Supreme Parent Group" profile information:
Figure 21. Memory Initialization File (.mif) with Dynamic Reconfiguration Recovery enabled Feature

If the design consists of 16 independent MRIPs, the .mif file displays the 16 supreme_parent_group_ids and their corresponding user_provided_ids.

The following is an example of the required register configuration sequence for the recovery process from any current state back to the startup profile for the "Supreme Parent Group" (User Provided ID = 0×1) to the next profile (Profile1 ID = 0×3).
  1. Restore back to startup mode; In this example, the startup mode is profile 1
    • avmm_write(32'h04, 32'h00060001); //dyn_rcfg_dr_next_profile_0_reg
    • avmm_write(32'h0, 32'h00000001); //trigger dynamic reconfiguration
  2. Trigger DR to target profile 3
    • avmm_write(32'h04, 32'h00040001); //bit[18] set to 1 in simulation to disable CPI sequence
    • avmm_write(32'h08, 32'h00008003); //dyn_rcfg_dr_next_profile_1_reg
    • avmm_write(32'h0, 32'h00000001);// trigger dynamic reconfiguration

If the recovery feature is not enabled and you attempt to run the recovery process, the dyn_rcfg_local_error_stat_ctrl_reg indicates the ERROR_CODE_29.

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