F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023
Public

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Document Table of Contents

5.1. Clocks

This section describes the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP clock domains.

The F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP and the corresponding soft CPU subsystem run on the free-running system clock. The system clock is independent from the transceiver clocks. Dynamically changing the transceiver reference clock does not impact the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP and the soft CPU.

The IP consists of 3 clock domains each represented by a different color in the figure below. All clock domain crossings within the IP are internally synchronized.
  • Clock Domain #1: Dynamic reconfiguration ports
  • Clock Domain #2: Avalon® memory-mapped interface arbiter (AVMM arbiter) and the dynamic reconfiguration (DR) CSRs
  • Clock Domain #3: Soft CPU including the Nios® core
Figure 25.  F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Clocking