F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Using QSF-driven Flow 4.4. Dynamic Reconfiguration Rules 4.5. Hardware States and Configuration Profiles 4.6. Nios® -Based Dynamic Reconfiguration Flow 4.7. Using the Tile Assignment Editor 4.8. Visualizing Dynamic Reconfiguration Group Placement 4.9. Assigning IP_COLOCATE Hierarchy 4.10. Example: Dynamic Reconfiguration with Multirate IP Flow 4.11. Example: Dynamic Reconfiguration Programming Sequence 4.12. Dynamic Reconfiguration Error Recovery Handling 4.13. Determining Profile Numbers 4.14. Master Clock Channel 4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment
4.6. Nios® -Based Dynamic Reconfiguration Flow x
4.6.1. Selecting the Nios® Data Memory Size
4.7. Using the Tile Assignment Editor x
4.7.1. Creating .qsf Assignments 4.7.2. Generating the IP_Colocate QSF Assignment
4.14. Master Clock Channel x
4.14.1. Selecting the Master Clock Channel 4.14.2. Automation for selecting the Master Clock Channel
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm 6.33. Dynamic Reconfiguration Local Error Status
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

4.7.1. Creating .qsf Assignments

  1. Create discrete IPs using the Platform Designer.
  2. Instantiate these IPs into your design using the appropriate RTL connections.
  3. Run Design Analysis on the design.
  4. Open the Tile Assignment Editor. Click on Intel® Quartus® Prime Menu > Assignments > Tile Assignment Editor.
  5. Click on new DR Group cell and define the properties for your DR group. Enter the attributes and click OK.
    Figure 6. New DR Group Properties
  6. Observe the IPs under the ungrouped IP Instances cell. Right-click on one of the ungrouped IPs and click on the Move IP Instance option.
    Figure 7. Ungrouped IP Instances
  7. Select an appropriate reconfiguration group for the IP and click OK.
    Figure 8. Selecting Reconfiguration Group
  8. Repeat step 6 and 7 for all the remaining ungrouped IPs.
  9. Right-click on reconfiguration group name under the grouped IP Instances cell. Select an IP to use for the Master Clock Channel using the Use master clock channel from: pulldown menu.
    Figure 9. Selecting an IP for Master Clock Channel
  10. Click on the IP under the reconfiguration group name that you want as a startup instance. Select the Is Startup Instance dialog button.
    Figure 10. Option: Startup Instance
  11. Click on Save Tile Assignment Editor.
    Note: The Master Clock Channel and Startup Instance is now defined in the Properties column of the Tile Assignment Editor.
    Figure 11. Properties
  12. Select the Reconfiguration Controller IP that the protocol IP should be associated with using the Reconfig controller pulldown menu.
  13. Click on Save Tile Assignment Editor to write all your newly derived dynamic reconfiguration assignments to your project’s .qsf file.
  14. Open the project’s .qsf file to verify the dynamic reconfiguration assignments.
    Sample: QSF Assignments for basic design with two instances of Multirate IPs. 
    set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_A:EXCLUSIVE:CLK_MASTER" -entity dr_mr_eth_mr_cpri_same_ux
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_A:MY_MR_CPRI_INST_1|CPRIPHY_MR_F_0/RG_A" -entity dr_mr_eth_mr_cpri_same_ux
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_A:MY_MR_ETH_INST_1|ETH_F_DR_0/RG_A" -entity dr_mr_eth_mr_cpri_same_ux
set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE OFF -to my_mr_eth_inst_1|eth_f_dr_0 -entity dr_mr_eth_mr_cpri_same_ux
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_mr_cpri_inst_1|cpriphy_mr_f_0 -entity dr_mr_eth_mr_cpri_same_ux
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_mr_eth_inst_1|eth_f_dr_0 -entity dr_mr_eth_mr_cpri_same_ux
set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL OFF -to my_mr_eth_inst_1|eth_f_dr_0 -entity dr_mr_eth_mr_cpri_same_ux
The above example illustrating a simple design using only two instances of Multirate IPs. You can use the Tile Assignment Editor to create more complex hierarchical DR groupings for designs which contain both multirate and single rate IPs. The figure below shows the Tile Assignment Editor GUI for such an advanced design:
Figure 12. Example: Advanced Design

The associated .qsf assignments for this example are shown below:

Sample: QSF Assignments for Advanced Design 
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e100g_4_1_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e100g_4_2_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e100g_4_3_inst_1|eth_f_0 -entity ceg_ex_v4

set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e25g_1_1_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e25g_1_2_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e25g_1_3_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e25g_1_4_inst_1|eth_f_0 -entity ceg_ex_v4

set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e25g_1_5_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e25g_1_6_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e25g_1_7_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e25g_1_8_inst_1|eth_f_0 -entity ceg_ex_v4

set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e25g_1_9_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_e25g_1_10_inst_1|eth_f_0 -entity ceg_ex_v4

set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_cpri25g_1_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_cpri25g_2_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4


set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_cpri25g_3_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_cpri25g_4_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4

set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_cpri25g_5_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_cpri25g_6_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4

set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_mr_e25g_inst_1|eth_f_dr_0 -entity ceg_ex_v4
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_mr_cpri24g_inst_1|cpriphy_mr_f_0 -entity ceg_ex_v4


set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_mr_cpri24g_2_inst_1|cpriphy_mr_f_0 -entity ceg_ex_v4

set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_mr_pma25g_inst_1|directphy_f_dr_0 -entity ceg_ex_v4

set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst_1|dr_f_0 -to my_pma25g_3_inst_1|directphy_f_0 -entity ceg_ex_v4

set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_A2:EXCLUSIVE" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_C1:INCLUSIVE" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_A1:EXCLUSIVE" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_C2:INCLUSIVE" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_B2:INCLUSIVE" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_A3:INCLUSIVE" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_A4:INCLUSIVE" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_D:EXCLUSIVE:CLK_MASTER" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_B1:EXCLUSIVE" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_B3:INCLUSIVE" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_A:RG_A1" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_A:RG_A2" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_A:RG_A3" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_A:RG_A4" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_B:RG_B1" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_B:RG_B2" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_B:RG_B3" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_C:RG_C1" -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_C:RG_C2" -entity ceg_ex_v4

set_instance_assignment -name IP_RECONFIG_GROUP RG_D -to my_pma25g_3_inst_1|directphy_f_0 -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_D:MY_MR_CPRI24G_INST_1|CPRIPHY_MR_F_0/RG_A" -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE OFF -to my_mr_cpri24g_inst_1|cpriphy_mr_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL OFF -to my_mr_cpri24g_inst_1|cpriphy_mr_f_0 -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_D:MY_MR_E25G_INST_1|ETH_F_DR_0/RG_A" -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE OFF -to my_mr_pma25g_inst_1|directphy_f_dr_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL OFF -to my_mr_pma25g_inst_1|directphy_f_dr_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_A1 -to my_e100g_4_1_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE ON -to my_e100g_4_1_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_A2 -to my_e100g_4_2_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_A3 -to my_cpri25g_1_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_A3 -to my_cpri25g_2_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_A4 -to my_e25g_1_1_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_A4 -to my_e25g_1_2_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_A4 -to my_e25g_1_3_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_A4 -to my_e25g_1_4_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_B1 -to my_e100g_4_3_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE ON -to my_e100g_4_3_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_B2 -to my_cpri25g_3_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_B2 -to my_cpri25g_4_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_B3 -to my_e25g_1_5_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_B3 -to my_e25g_1_6_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_C1 -to my_cpri25g_5_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_C1 -to my_cpri25g_6_inst_1|cpriphy_ftile_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_C2 -to my_e25g_1_7_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE ON -to my_e25g_1_7_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_C2 -to my_e25g_1_8_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_C2 -to my_e25g_1_9_inst_1|eth_f_0 -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP RG_C2 -to my_e25g_1_10_inst_1|eth_f_0 -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_B:EXCLUSIVE:CLK_MASTER" -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL "PLD_PCS_TX_CLK_OUT1_DCM:RG_B" -to my_e100g_4_3_inst_1|eth_f_0|hip_inst|per_aib[0].x_bb_m_hdpldadapt_tx -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_C:EXCLUSIVE:CLK_MASTER" -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL "PLD_PCS_TX_CLK_OUT1_DCM:RG_C" -to my_e25g_1_7_inst_1|eth_f_0|hip_inst|per_aib[0].x_bb_m_hdpldadapt_tx -entity ceg_ex_v4
set_global_assignment -name IP_RECONFIG_GROUP_TYPE "RG_A:EXCLUSIVE:CLK_MASTER" -entity ceg_ex_v4
set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL "PLD_PCS_TX_CLK_OUT1_DCM:RG_A" -to my_e100g_4_1_inst_1|eth_f_0|hip_inst|per_aib[0].x_bb_m_hdpldadapt_tx -entity ceg_ex_v4

set_global_assignment -name IP_RECONFIG_GROUP_PARENT "RG_D:MY_MR_PMA25G_INST_1|DIRECTPHY_F_DR_0/RG_A_E" -entity ceg_ex_v4
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