F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment

Table 43.   dyn_rcfg_dr_tx_fully_reset_ack_reg
Offset 0x60
Addressing Mode 32-bits
Description Dynamic reconfiguration status register.
Table 44.   dyn_rcfg_dr_tx_fully_reset_ack_reg Field Description
Bit Type Reset Description
31:20 RO 0 Reserved
19:0 RO 0 TX Channel is Fully in Reset State

Indicates the TX channel is fully in a reset state.

Fully in TX reset state status[N] = i_tx_lane_current_state[(19-N)*3+0] , where N is the number of channels from 0 to 19.

  • N = 0-3: FHT channels 0-3
  • N = 4-19: FGT channels 0-15