F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023
Public

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Document Table of Contents

5.2. Reset

This section describes the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP reset domains.
The IP provides multiple reset domains:
  • Reset Domain #1: Dynamic reconfiguration multiplexer (DR Mux), dynamic reconfiguration control status registers (DR CSR), Avalon® memory-mapped interface arbiter (AVMM arbiter), and the soft CPU reside in the same reset domain. This allows the IP to hold context such as DR port mapping to the EMIB channel in reset, even though the respective DR ports or EMIB channels are being reset as a part of the DR process.

    After power on, you must once assert and deassert this reset domain. Once completed, do not put the domain into reset again. The dynamic reconfiguration can only be executed after this reset domain is released.

    While this domain is in reset, the reset domains for the protocol IP(s) in the dynamic reconfiguration groups must stay asserted.

  • Port-Based Reset Domain: Each DR port has a dedicated reset pin. The pins are then muxed similar to the corresponding control and data pins.
Figure 26.  F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Reset

You must bring the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP out from reset prior to any other soft IPs.