F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

Download PDF
ID 711009
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Using QSF-driven Flow 4.4. Dynamic Reconfiguration Rules 4.5. Hardware States and Configuration Profiles 4.6. Nios® -Based Dynamic Reconfiguration Flow 4.7. Using the Tile Assignment Editor 4.8. Visualizing Dynamic Reconfiguration Group Placement 4.9. Assigning IP_COLOCATE Hierarchy 4.10. Example: Dynamic Reconfiguration with Multirate IP Flow 4.11. Example: Dynamic Reconfiguration Programming Sequence 4.12. Dynamic Reconfiguration Error Recovery Handling 4.13. Determining Profile Numbers 4.14. Master Clock Channel 4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment
4.6. Nios® -Based Dynamic Reconfiguration Flow x
4.6.1. Selecting the Nios® Data Memory Size
4.7. Using the Tile Assignment Editor x
4.7.1. Creating .qsf Assignments 4.7.2. Generating the IP_Colocate QSF Assignment
4.14. Master Clock Channel x
4.14.1. Selecting the Master Clock Channel 4.14.2. Automation for selecting the Master Clock Channel
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm 6.33. Dynamic Reconfiguration Local Error Status
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

4.14. Master Clock Channel

The F-Tile Dynamic Reconfiguration requires the IPs to be in System PLL Clocking mode. All dynamic reconfiguration profiles in a dynamic reconfiguration group must use the same System PLL Clock frequency value.

When operating in System PLL Clocking mode, the F-tile IPs are standardized to source the datapath clock from the F-tile via pld_pcs_tx_clk_out1_dcm (duplex and TX simplex) or pld_pcs_rx_clk_out1_dcm (RX simplex). The soft IP datapath is expected to be clocked by System PLL DIV2 clock.

For dynamic reconfiguration, the Intel® Quartus Support Logic Generation connects the selected master clock channel to clock the soft IP datapath and feed it to the F-tile. Choose the master clock channel so that it is stable. Otherwise, it can cause disruption to the protocol IP operation during dynamic reconfiguration.

You can specify the master clock channel via QSF assignment. The Multirate IPs specify the master clock channel in their respective .qip files. You can override this setting in the .qip file using the QSF assignment. If the master clock channel is not specified by either a QSF assignment or a setting within the .qip file, the Quartus Support Logic Generation automatically sources the master clock from the corresponding System PLL DIV2 port.

The .qsf assignment used to select the master clock channel is shown below:

set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL -to <bb_instance_hpath> <clock-port-name>

The following clock port names are allowed:
  • For duplex and TX simplex mode: PLD_PCS_TX_CLK_OUT1_DCM
  • For RX simplex mode: PLD_PCS_RX_CLK_OUT1_DCM
When you use one of the Multirate IPs in your design, each Multirate .qip file contains a master clock channel group assignment. Examples of each Multirate IP are shown below:
  • CPRI PHY Multirate IP:
    • set_instance_assignment -entity test_cpri_mr_cpriphy_mr_f_310_alqii3y -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL PLD_PCS_TX_CLK_OUT1_DCM -to profile_0|cpriphy_ftile_0|cpriphy_f_bb_inst|hip_bb|bb_m_hdpldadapt_tx_inst0
  • Ethernet Multirate IP:
    • set_instance_assignment -entity test_ethernet_mr_eth_f_dr_500_sfnvzqy -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL PLD_PCS_TX_CLK_OUT1_DCM -to U_base_profile|eth_f_0|hip_inst|per_aib[0].x_bb_m_hdpldadapt_tx
  • Direct PHY Multirate IP:
    • set_instance_assignment -entity test_dphy_mr_directphy_f_dr_202_sok7rvy -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL PLD_PCS_TX_CLK_OUT1_DCM -to U_base_profile|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].peraib[0].tx_aib.x_bb_m_hdpldadapt_tx

For dynamic reconfiguration, the master clock channel selects the PLD_PCS_TX_CLK_OUT1_DCM clock source in the multirate .QIP; in other words, the system PLL DIV2 clock can only be sourced from the pld_pcs_tx_clkout1_dcm (except for RX simplex mode).

The following scenarios that might require you to manually specify the master clock channel at the design level via QSF:
  1. Design with multiple Multirate IPs are used in the same dynamic reconfiguration group.
    1. For example, if Ethernet Multirate IP and CPRI PHY Multirate IP are in the same DR group, you must specify which IP the master clock should be sourced from and disable the master clock for the other IP.
    2. The following example shows how to enable the master clock from Ethernet Multirate IP and disable the master clock selection from CPRI PHY Multirate IP.
      • set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL OFF -to cpri_ed_inst -entity eth_cpriphy_f_hw
      • set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL PLD_PCS_TX_CLK_OUT1_DCM -to eth_ed_inst|hw_ip_top|dut|eth_f_dr_0|U_base_profile|eth_f_0|hip_inst|per_aib[0].x_bb_m_hdpldadapt_tx -entity eth_cpriphy_f_hw
  2. DR design which only uses Single Rate IP.
    1. Unlike the Multirate IP, there is no master clock channel assignment pre-set in the Single Rate IP .qip file.
    2. You need to manually define the master clock channel source assignment in the design level QSF file. Otherwise, the Quartus Tile Logic Generation(QTLG) sources the master clock automatically from the corresponding System PLL DIV2 port.
  3. The master clock in a dynamic reconfiguration design is sourced externally from the dynamic reconfiguration group.
    1. You must choose an appropriate master clock source (it must be a constant clock that is with System PLL Div2 clock frequency originated from the same System PLL used by the DR group). In a typical scenario, you source the clock from another IP that does not perform dynamic reconfiguration in order to provide a constant clock to the dynamic reconfiguration group by manually assigning the master clock source assignment in the design QSF file.

    For example, consider a design that includes two Direct PHY Multirate IP instances, each having its own master clock sourced from a "dummy" Direct PHY Multirate IP.

    The following are the QSF settings:
    • set_global_assignment -name IP_RECONFIG_GROUP_TYPE "TEST_GROUP:INCLUSIVE:CLK_MASTER" -entity devkit_demo
    • set_global_assignment -name IP_RECONFIG_GROUP_PARENT "TEST_GROUP:GENENERATE_TRANSCEIVER_BLOCK[0].INSTX|GENERATE_PHY_DIRECT[0].MRIP_INST|DIRECTPHY_F_DR_0/RG_A_E” -entity devkit_demo
    • set_global_assignment -name IP_RECONFIG_GROUP_PARENT "TEST_GROUP:GENENERATE_TRANSCEIVER_BLOCK[0].INSTX|GENERATE_PHY_DIRECT[1].MRIP_INST|DIRECTPHY_F_DR_0/RG_A_E” -entity devkit_demo
    • set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL “PLD_PCS_TX_CLK_OUT1_DCM:TEST_GROUP” -to dummy_tx_inst:directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].peraib[0].tx_aib.x_bb_m_hdpldadapt_tx
  4. Ethernet and PTP Multirate IP variant:
    1. By default, the Ethernet Multirate IP QIP settings assign the master clock source to its bb_m_hdpldadapt_tx.
      • set_instance_assignment -entity ex_25G_mr_eth_f_dr_500_sfnvzqy -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL PLD_PCS_TX_CLK_OUT1_DCM -to U_base_profile|eth_f_0|hip_inst|per_aib[0].x_bb_m_hdpldadapt_tx
    2. For the PTP-enabled variant, change the master clock channel source to PTP AIB channel 7 as shown below.
      • set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL OFF -to IP_INST[0].hw_ip_top|dut|eth_f_dr_0 -entity eth_f_hw
      • set_instance_assignment -entity test_ethernet_mr_eth_f_dr_500_sfnvzqy -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL “PLD_PCS_TX_CLK_OUT1_DCM:IP_INST[0].HW_IP_TOP|DUT|ETH_F_DR_0/RG_A” -to ptp_adpt_f|hip_inst|x_bb_m_hdpldadapt_tx_ch7 -entity eth_f_hw

Section Content
Selecting the Master Clock Channel
Automation for selecting the Master Clock Channel

Level Two Title