Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/30/2024
Public
Document Table of Contents

2.1.2. Root Port Mode

  • MCDMA H-Tile: PCIe Gen3 x16/x8 in Stratix® 10 GX and Stratix® 10 MX devices
  • MCDMA P-Tile: PCIe Gen4/Gen3 x16 and 4x4 ports in Stratix® 10 DX and Agilex™ 7 devices
  • MCDMA F-Tile: PCIe Gen4/Gen3 x16/x8, 2x4 and 4x4 in Agilex™ 7 device
  • MCDMA R-Tile:
    • PCIe Gen5/Gen4/Gen3 2x8 ports in Agilex™ 7 devices.
    • PCIe Gen4/Gen3 x16 and Gen5/Gen4/Gen4 4x4 ports only in Agilex™ 7 I-Series FPGA Development Kit DK-DEV-AGI027R1BES R-Tile B0 revision.
  • Configuration Slave (CS) interface for accessing Endpoint’s config space
  • Address Translation Table (ATT) is supported in BAS mode. MCDMA H-Tile IP does not support ATT.
  • User mode options:
    • Bursting Avalon Master (BAM)
    • Bursting Avalon Slave (BAS)
    • BAM and BAS
  • Ports subdivided 4x4 can run independently and concurrently (separately) instances on AVMM IP for R-Tile MCDMA Agilex™ 7 device
    • Examples: Port0 -> BAM, Port1 -> BAM+BAS, Port2 -> BAS & Port3 -> BAM+BAS.
    • Each instance runs independently with separate PERST
    • Only SCT is supported
  • Ports subdivided 2x4 or 4x4 can run independently and concurrently (separately) instances on AVMM IP for F-Tile MCDMA Agilex™ 7 device
    • Each instance runs independently with separate PERST
    • Only SCT is supported
  • Maximum payload size supported:
    • Stratix® 10 GX and Stratix® 10 MX devices: 512 bytes
    • Stratix® 10 DX and Agilex™ 7 devices: 512 / 256 / 128 bytes