Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/30/2024
Public
Document Table of Contents

8.2.6. API Flow

The flow between the Host software components and hardware components is depicted in below sequence diagram for Host to Device data transfer.

Figure 53. Host to Device Sequence

The flow between the Host software components and hardware components is depicted in below sequence diagram for Device to Host data transfer.

Figure 54. Device to Host Sequence