Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/30/2024
Public
Document Table of Contents

6.2.4.10. Receiver Detection (F-Tile MCDMA IP Only)

Table 91.  Receiver Detection Parameters (F-Tile MCDMA IP Only)
Parameter Value Default Value Description
PF0 FORCE_DETECT_LANE enable True/False False

Force Detect Lane Enable

When this option is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE value

PF0 FORCE_DETECT_LANE value 0x0000ffff - 0x00000000 0x00000000
When the FORCE_DETECT_LANE_EN field is set, the controller ignores receiver detetction from PHY during LTSSM Detect state and uses this value instead:
  • For x4 lane: 0x0000000f
  • For x8 lane: 0x000000ff
  • For x16 lane: 0x0000ffff