Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/30/2024
Public
Document Table of Contents

4.2.1. F-Tile System PLL Reference Clock Requirements

The F-Tile Reference and System PLL Clocks Intel FPGA IP is required IP for MCDMA F-Tile designs to configure the reference clock for the PCI Express channels and configure the System PLL.

Reference clock to the System PLL can be driven to any one of the F-Tile reference clock pins, refclk[0] to refclk[7]. The reference clock must adhere to the following requirements:
  • If compliance to PCI Express link training timing specifications are required, the reference clock to System PLL must be available and stable before device configuration begins. You must set the Refclk is available at power-on parameter in the System PLL IP to On. Derive the reference clock from an independent and free running clock source. Alternately, if the reference clock from the PCIe link is guaranteed available before device configuration begins, you can use it to drive the System PLL. Once the PCIe link refclk is alive, it is never allowed to go down.
  • If compliance to PCI Express link training timing specifications are not required and the reference clock to System PLL may not be available before device configuration begins, you must set the Refclk is available at power-on parameter in the System PLL IP to Off. In this case, you may use the reference clock from the PCI Express link to drive the System PLL. The System PLL does not lock to the reference until you perform the Global Avalon memory-mapped interface write operations signaling that the reference clock is available.

Once the reference clock for the System PLL is up, it must be stable and present throughout the device operation and must not go down. If you are not able to adhere to this requirement, you must reconfigure the device.

Note: Refer to Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP section in F-Tile Architecture and PMA and FEC Direct PHY IP User Guide for information about this IP.
Note: Refer to Example Flow to Indicate All System PLL Reference Clocks are Ready section in F-Tile Architecture and PMA and FEC Direct PHY IP User Guide to trigger the System PLL to lock to reference clock.