AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

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ID 683803
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families x
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview x
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices x
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example x
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis x
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

System Setup

Figure 15. Multipoint BLVDS with Cyclone III BLVDS TransceiversThis figure shows the schematic of a multipoint topology with ten Cyclone® III BLVDS transceivers (named U1 to U10).


The bus transmission line is assumed to have the following characteristics:

  • A stripline
  • Characteristic impedance of 50 Ω
  • Characteristic capacitance of 3.6 pF per inch
  • Length of 10 inches
  • Bus differential characteristic impedance of approximately 100 Ω
  • Spacing between each transceiver of 1 inch
  • Bus terminated at both ends with termination resistor RT

In the example shown in the preceding figure, the fail-safe biasing resistors of 130 kΩ and 100 kΩ pulls the bus to a known state when all the drivers are tri-stated, removed, or powered off.

To prevent excessive loading to the driver and waveform distortion, the magnitude of the fail-safe resistors must be one or two orders higher than RT. To prevent a large common-mode shift from occurring between the active and tri-state bus conditions, the mid-point of the fail-safe bias must be close to the offset voltage of the driver (+1.25 V). You can power up the bus with the common power supplies (VCC).

Cyclone® III, Cyclone® IV, and Intel® Cyclone® 10 LP BLVDS transceivers are assumed to have the following characteristics:

  • Default drive strength of 12 mA
  • Slow slew rate settings by default
  • Pin capacitance of each transceiver of 6 pF
  • Stub on each BLVDS transceiver is a 1-inch microstrip of characteristic impedance of 50 Ω and characteristic capacitance of 3 pF per inch
  • Capacitance of the connection (connector, pad, and via in PCB) of each transceiver to the bus is assumed to be 2 pF
  • Total capacitance of each load is approximately 11 pF

For 1-inch load spacing, the distributed capacitance is equal to 11 pF per inch. To reduce reflection caused by the stubs, and also to attenuate the signals coming out of the driver, an impedance matching 50 Ω resistor RS is placed at the output of each transceiver.

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