AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

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ID 683803
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families x
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview x
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices x
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example x
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis x
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Driver Slew Rate

A fast slew rate helps to improve the rise time, especially at the receiver furthest from the driver. However, a faster slew rate also magnifies ringing due to reflection.
Figure 22. Effect of Driver Edge Rate (Driver in U1, Receiver in U2 and U10)This figure shows the driver slew rate effect. A comparison is made between the slow and fast slew rate with a 12 mA drive strength. The driver is at U1 and the differential waveforms at U2 and U10 are examined.


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