AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

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ID 683803
Date 7/31/2018
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Document Table of Contents
Document Table of Contents x
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families x
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview x
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices x
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example x
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis x
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Bus Termination

The effective impedance of the fully loaded bus is 52 Ω if you substitute the bus characteristic capacitance and the distributed capacitance per unit length of the setup into the effective differential impedance equation. For optimum signal integrity, you must match RT to 52 Ω.

The following figures show the effects of matched-, under-, and over-termination on the differential waveform (VID) at the receiver input pins. The data rate is 100 Mbps. In these figures, under-termination (RT = 25 Ω) results in reflections and significantly reduction of the noise margin. In some cases, under termination even violates the receiver threshold (VTH = ±100 mV). When RT is changed to 50 Ω, there is a substantial noise margin with respect to VTH and the reflection is negligible.

Figure 16. Effect of Bus Termination (Driver in U1, Receiver in U2)In this figure, U1 acts as the transmitter and U2 to U10 are the receivers.


Figure 17. Effect of Bus Termination (Driver in U1, Receiver in U10)In this figure, U1 acts as the transmitter and U2 to U10 are the receivers.


Figure 18. Effect of Bus Termination (Driver in U5, Receiver in U6)In this figure, U5 is the transmitter and the rest are receivers.


Figure 19. Effect of Bus Termination (Driver in U5, Receiver in U10)In this figure, U5 is the transmitter and the rest are receivers.


The relative position of the driver and receiver on the bus also affects the received signal quality. The nearest receiver to the driver experiences the worst transmission line effect because at this location, the edge rate is the fastest. This is made worse when the driver is located at the middle of the bus.

For example, compare Figure 16 and Figure 18. VID at receiver U6 (driver at U5) shows larger ringing than that at receiver U2 (driver at U1). On the other hand, the edge rate is slowed down when the receiver is located further away from the driver. The largest rise time recorded is 1.14 ns with the driver located at one end of the bus (U1) and the receiver at the other end (U10).

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