AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

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ID 683803
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families x
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview x
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices x
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example x
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis x
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Document Version Changes
2018.07.31
  • Removed Intel® Cyclone® 10 GX devices from the design example guidelines. Although Intel® Cyclone® 10 GX devices support BLVDS, the design examples in this application note do not support Intel® Cyclone® 10 GX devices.
  • Corrected the design examples guideline for Intel® Arria® 10 devices to specify that the design example steps are only supported for Intel® Quartus® Prime Standard Edition, not Intel® Quartus® Prime Pro Edition.
2018.06.15
  • Added support for Intel® Stratix® 10 devices.
  • Updated related information links.
  • Rebranded Intel FPGA GPIO IP to GPIO Intel FPGA IP.
Date Version Changes
November 2017 2017.11.06
  • Added support for Intel® Cyclone® 10 LP devices.
  • Updated related information links.
  • Updated I/O standard names to follow standard usage.
  • Rebranded as Intel, including names of devices, IP cores, and software tools, where applicable.
May 2016 2016.05.02
  • Added support and design example for Intel® MAX® 10 devices.
  • Restructured several sections to improve clarity.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.09
  • Updated the design example files.
  • Updated design example guidelines:
    • Moved the steps for Arria 10 devices into a new topic.
    • Added steps to migrate the design examples to use Altera GPIO IP core for Arria 10 devices.
    • Updated the design example steps to match the updated design examples.
  • Updated all links to updated website location and web-based documentation (if available).
August 2014 2014.08.18
  • Updated application note to add Arria 10 device support.
  • Restructured and rewrote several sections for clarity and style update.
  • Updated template.
June 2012 2.2
  • Updated to include Arria II, Arria V, Cyclone V, and Stratix V devices.
  • Updated Table 1 and Table 2.
April 2010 2.1 Updated the design example link in the “Design Example” section.
November 2009 2.0
  • Included Arria II GX, Cyclone III, and Cyclone IV device families in this application note.
  • Updated Table 1,Table 2, and Table 3.
  • Update Figure 5, Figure 6, Figure 8 through Figure 11.
  • Updated design example files.
November 2008 1.1
  • Updated to new template
  • Updated "BLVDS Technology in Altera Devices" chapter
  • Updated "Power Consumption of BLVDS" chapter
  • Updated "Design Example" chapter
  • Replaced Figure 4 on page 7
  • Updated "Design Example Guidelines" chapter
  • Updated "Performance Analysis" chapter
  • Updated "Bus Termination" chapter
  • Updated "Summary" chapter
July 2008 1.0 Initial release.
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