AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

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ID 683803
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families x
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview x
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices x
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example x
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis x
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Effective Impedance

The effective impedance depends on the bus trace characteristic impedance Zo and capacitive loading on the bus. The connectors, the stub on the plug-in card, the packaging, and the receiver input capacitance all contribute to capacitive loading, which reduces the bus effective impedance.
Equation 1. Effective Differential Impedance EquationUse this equation to approximate the effective differential impedance of the loaded bus (Zeff).


Where:

  • Zdiff (Ω) ≈ 2 × Zo = the differential characteristic impedance of the bus
  • Co (pF/inch) = characteristic capacitance per unit length of the bus
  • CL (pF) = capacitance of each load
  • N = number of loads on the bus
  • H (inch) = d × N = total length of the bus
  • d (inch) = spacing between each plug-in card
  • Cd (pF/inch) = CL/d = distributed capacitance per unit length across the bus

The increment in load capacitance or closer spacing between the plug-in cards reduces the effective impedance. To optimize the system performance, it is important to select a low capacitance transceiver and connector. Keep each receiver stub length between the connector and transceiver I/O pin as short as possible.

Figure 2. Normalized Effective Impedance Versus Cd/Co This figure shows the effects of distributed capacitance on normalized effective impedance.


Termination is required at each end of the bus, while the data flows in both directions. To reduce reflection and ringing on the bus, you must match the termination resistor to the effective impedance. For a system with Cd/Co = 3, the effective impedance is 0.5 times of Zdiff. With double terminations on the bus, the driver sees an equivalent load of 0.25 times of Zdiff; and thus reduces the signals swing and differential noise margin across the receiver inputs (if standard LVDS driver is used). The BLVDS driver addresses this issue by increasing the drive current to achieve similar voltage swing at the receiver inputs.

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