AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

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ID 683803
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families x
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview x
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices x
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example x
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis x
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Performance Analysis

The multipoint BLVDS performance analysis demonstrates the impact of the bus termination, loading, driver and receiver characteristics, and the location of the receiver from the driver on the system.

You can use the included BLVDS design examples to analyze the performance of a multipoint application:

  • Cyclone® III BLVDS design example—this design example is applicable to all supported Stratix® , Arria® , and Cyclone® device series. For Intel® Arria® 10 or Intel® Cyclone® 10 GX device family, you need to migrate the design example to the respective device family first before you can use it.
  • Intel® MAX® 10 BLVDS design example—this design example is applicable to Intel® MAX® 10 device family.
  • Intel® Stratix® 10 BLVDS design example—this design example is applicable to Intel® Stratix® 10 device family.
Note: The performance analysis of a multipoint BLVDS in this section is based on the Cyclone® III BLVDS input/output buffer information specification (IBIS) model simulation in HyperLynx*.

Intel recommends that you use these Intel® IBIS models for simulation:

  • Stratix® III, Stratix® IV, and Stratix® V devices—device-specific Differential SSTL-2 IBIS model
  • Intel® Stratix® 10, Intel® Arria® 10 2 and Intel® Cyclone® 10 GX devices:
    • Output buffer—Differential SSTL-18 IBIS model
    • Input buffer—LVDS IBIS model

Section Content
System Setup
Bus Termination
Stub Length
Stub Termination
Driver Slew Rate
Overall System Performance

Related Information
2 The Intel® Arria® 10 IBIS models are preliminary and are not available on the Intel® IBIS model web page. If you require these preliminary Intel® Arria® 10 IBIS models, contact Intel.
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