AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Download PDF
ID 683803
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families x
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview x
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices x
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example x
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis x
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

BLVDS Power Consumption

In comparison to other high-performance bus technologies such as Gunning Transceiver Logic (GTL), which uses more than 40 mA, BLVDS typically drives out current in the range of 10 mA. For example, based on the Cyclone® III Early Power Estimator (EPE) estimation for typical power characteristics of Cyclone® III devices in an ambient temperature of 25° C, the average power consumption of a BLVDS bidirectional buffer at a data rate of 50 MHz and an output enabled 50% of the time is approximately 17 mW.
  • Before implementing your design into the device, use the Excel-based EPE for the supported device you use to get an estimated magnitude of the BLVDS I/O power consumption.
  • For input and bidirectional pins, the BLVDS input buffer is always enabled. The BLVDS input buffer consumes power if there is switching activity on the bus (for example, other transceivers are sending and receiving data, but the Cyclone® III device is not the intended recipient).
  • If you use BLVDS as an input buffer in multidrop or as a bidirectional buffer in multipoint applications, Intel recommends entering a toggle rate that includes all activities on the bus, not just activities intended for the Intel device BLVDS input buffer.
Figure 5. Example of BLVDS I/O Data Entry in the EPEThis figure shows the BLVDS I/O entry in the Cyclone® III EPE. For I/O standards to select in the EPE of other supported Intel® devices, refer to the related information.


Intel recommends that you use the Intel® Quartus® Prime Power Analyzer Tool to perform an accurate BLVDS I/O power analysis after you complete your design. The Power Analyzer Tool estimates power based on the specifics of the design after place-and-route is completed. The Power Analyzer Tool applies a combination of user-entered, simulation-derived, and estimated signal activities which, combined with the detailed circuit models, yields very accurate power estimates.

Related Information
Level Two Title