AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

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ID 683803
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families x
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview x
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices x
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example x
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis x
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Design Example Guidelines for Intel® MAX® 10 Devices

These steps are applicable to Intel® MAX® 10 devices only. Ensure that you use the GPIO Lite Intel® FPGA IP core.
  1. Create an GPIO Lite Intel® FPGA IP core that can support a bidirectional input and output buffer:
    1. Instantiate the GPIO Lite Intel® FPGA IP core.
    2. In Data Direction, select Bidir.
    3. In Data width, enter 1.
    4. Turn on Use pseudo differential buffer.
    5. In Register mode, select Bypass.
  2. Connect the modules and the input and output ports as shown in the following figure:
    Figure 10. Input and Output Ports Connection Example for Intel® MAX® 10 Devices


  3. In the Assignment Editor, assign the relevant I/O standard as shown in the following figure. You can also set the current strength and slew rate options. Otherwise, the Intel® Quartus® Prime software assumes the default settings.
    Figure 11. BLVDS I/O Assignment in the Intel® Quartus® Prime Assignment Editor for Intel® MAX® 10 Devices


  4. Compile and perform functional simulation with the ModelSim* - Intel® FPGA Edition software.
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